STEVAL-IPE008V1 STMicroelectronics, STEVAL-IPE008V1 Datasheet - Page 34

• Manufacturer Part Number: STEVAL-IPE008V1
• Description: BOARD EVAL STPM01/STR715FR0
• Manufacturer: STMicroelectronics
• Type: Other Power Managementr

Specifications of STEVAL-IPE008V1

• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, ARM7
• Utilized Ic / Part: STPM01, STR715FR0
• Primary Attributes: 3-Ph Energy Meter (or Single Phase)
• Secondary Attributes: Measures Active, Reactive, Apparent Power
• Product: Power Management Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: STPM01, STR715FR0
• Other names: 497-6412; STEVAL-IPE008V1

Theory of operation
Table 16.
34/60
000000
000001
000010
000011
000100
binary
6-bit
Address
DEC
4
0
1
2
3
(1)
The very first CFG bit, called TSTD, is used to disable any change of system signals after it
was permanently set. During the configuration phase, each bit set to logic level 1 will
increase the supply current of STPM01 of about 120 µA, until the TSTD bit is set to 1. The
residual increase of supply current is 2 µA per each bit set to 1. It is then recommended to
set the TSTD bit to 1 after the configuration procedure in order to keep the supply current as
low as possible.
The STPM01 can work either using the data stored in the OTP cells either the data available
in the shadow latches. This can be chosen according to the value RD Mode signal (see
mode signal paragraph for description). If the RD is set, the CFG bits originates from
corresponding OTP shadow latches otherwise, if the RD is cleared, the CFG bits originates
from corresponding OTP antifuses. This way one can temporary sets up certain
configuration or calibration of device then verify it and then change it, if it is necessary. For
example, this is extensively exercised during production tests.
Each configuration bit can be written sending a byte command to STPM01 through its SPI
interface. The procedure to write the configuration bits is described in the SPI section.
After the TSTD bit has been set, the only write commands accepted will be the precharge
and the remote reset, this implies that the shadow latches cannot be used as source of
configuration data anymore.
Configuration bits map
Name
TSTD
MDIV
APL
RC
n. of
bits
1
1
1
2
Test mode and OTP write disable:
- TSTD=0: testing and continuous pre-charge of OTP when in read mode,
- TSTD=1:normal operation and no more writes to OTP
Measurement frequency range selection:
- MDIV=0: 4.000MHz to 4.194MHz,
- MDIV=1: 8.000MHz to 8.192MHz
Type of internal oscillator selection:
- RC=0:crystal oscillator,
- RC=1:RC oscillator
Peripheral or Standalone mode:
- APL=0: peripheral, MON=WatchDOG; MOP=ZCR, LED=pulses,
- APL=1: peripheral, MOP=ΔΣ Voltage; MON=ΔΣ current; LED=Mux (current) -
APL=2: standalone, MOP,MON=stepper, LED=pulses, SCLNLC=no load
condition, SDATD=tamper detected, SYN=negative active power direction
- APL=3: standalone, MOP:MON=stepper, LED=pulses according to KMOT,
SCLNLC=no load condition, SDATD=tamper detected, SYN=negative active
power direction
Doc ID 10853 Rev 7
Description
(1)
STPM01