CP2201EK Silicon Laboratories Inc, CP2201EK Datasheet - Page 96

• Manufacturer Part Number: CP2201EK
• Description: KIT EVAL FOR CP2201 ETH CTRLR
• Manufacturer: Silicon Laboratories Inc
• Type: Controllers & Processorsr

Specifications of CP2201EK

• Main Purpose: Interface, Ethernet Sensor
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: CP2200, CP2201
• Primary Attributes: Temperature and Light Sensor
• Secondary Attributes: Graphic User Interface
• Interface Type: Ethernet
• Product: Modules
• Silicon Manufacturer: Silicon Labs
• Silicon Core Number: CP2201
• Silicon Family Name: CP220x
• Kit Contents: CP2201 Evaluation Board, Power Adapter, CAT5e Ethernet Cable, CD-ROM, Quick-Start Guide
• For Use With/related Products: CP2201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 336-1316

CP2200/1
16. Parallel Interface
The CP2200/1 has an 8-bit parallel host interface used to access the direct registers on the device. The parallel
interface supports multiplexed or non-multiplexed operation using the Intel
pin can be driven high to place the device in multiplexed operation or driven low to select non-multiplexed
operation. The MOTEN pin can be driven high to place the device in Motorola bus format or driven low to place the
device in Intel bus format.
Notes:
A parallel interface read or write operation typically requires 260 ns (non-multiplexed) or 300 ns (multiplexed) to
transfer one byte of data. If back-to-back operations are scheduled on a non-multiplexed bus, data rates up to
30 Mbps can be achieved. Tables 26 through 29 provide detailed information about bus timing in each mode.
16.1. Non-Multiplexed Intel Format
96
1. The CP2201 (28-pin package) can only be used in multiplexed mode.
2. The PCB traces connecting RD, WR, CS, ALE, and all address and data lines should be matched such that the
propagation delay does not vary by more than 5 ns between any two signals.
D[7:0]
Notes:
1. CS must be asserted with or before RD.
2. WR must remain de-asserted during a READ.
D[7:0]
A[7:0]
A[7:0]
Notes:
1. CS must be asserted with or before WR.
2. RD must remain de-asserted during a WRITE.
WR
RD
Figure 22. Nonmuxed Intel READ
T
T
AS
AS
Rev. 1.0
Valid Address
Valid Address
T
VD1
T
T
RD
WR
T
DS
Valid Data
Valid Data
T
T
®
AHR
AHW
T
T
VD2
or Motorola
DH
T
T
HOLD
HOLD
®
bus format. The MUXEN