STEVAL-IFS006V1 STMicroelectronics, STEVAL-IFS006V1 Datasheet - Page 35
![BOARD EVAL 8BIT MICRO + TDE1708](/photos/9/19/91986/steval-ifs006v1_sml.jpg)
STEVAL-IFS006V1
Manufacturer Part Number
STEVAL-IFS006V1
Description
BOARD EVAL 8BIT MICRO + TDE1708
Manufacturer
STMicroelectronics
Datasheets
1.TDE1708DFT.pdf
(14 pages)
2.STEVAL-IFS006V1.pdf
(136 pages)
3.STEVAL-IFS006V1.pdf
(4 pages)
Specifications of STEVAL-IFS006V1
Design Resources
STEVAL-IFS006V1 Bill of Material
Sensor Type
Proximity
Interface
I²C
Voltage - Supply
6 V ~ 48 V
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
ST7FLITEUS5, TDE1708
Processor To Be Evaluated
ST7LITEUS5
Data Bus Width
8 bit
Operating Supply Voltage
6 V to 48 V
Silicon Manufacturer
ST Micro
Silicon Core Number
TDE1708DFT
Kit Application Type
Sensing - Touch / Proximity
Application Sub Type
Proximity Switch
Kit Contents
Board
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Sensitivity
-
Sensing Range
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-6403
STEVAL-IFS006V1
STEVAL-IFS006V1
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
ST7LITEUS2, ST7LITEUS5
6.4
6.4.1
Note:
Caution:
Reset sequence manager (RSM)
Introduction
The reset sequence manager includes three reset sources as shown in
●
●
●
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.
The basic reset sequence consists of 3 phases as shown in
●
●
●
When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
The 64 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery
has taken place from the Reset state.
The RESET vector fetch phase duration is 2 clock cycles.
Figure 11. Reset sequence phases
External RESET source pulse
Internal LVD reset (low voltage detection)
Internal WATCHDOG reset
Active phase depending on the reset source
64 CPU clock cycle delay
RESET vector fetch
Figure
12.
Active phase
64 CLOCK CYCLES
INTERNAL RESET
RESET
Supply, reset and clock management
VECTOR
FETCH
Figure
11:
Figure
12:
35/136