STEVAL-IFS006V1 STMicroelectronics, STEVAL-IFS006V1 Datasheet - Page 81

• Manufacturer Part Number: STEVAL-IFS006V1
• Description: BOARD EVAL 8BIT MICRO + TDE1708
• Manufacturer: STMicroelectronics

Specifications of STEVAL-IFS006V1

• Design Resources: STEVAL-IFS006V1 Bill of Material
• Sensor Type: Proximity
• Interface: I²C
• Voltage - Supply: 6 V ~ 48 V
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ST7FLITEUS5, TDE1708
• Processor To Be Evaluated: ST7LITEUS5
• Data Bus Width: 8 bit
• Operating Supply Voltage: 6 V to 48 V
• Silicon Manufacturer: ST Micro
• Silicon Core Number: TDE1708DFT
• Kit Application Type: Sensing - Touch / Proximity
• Application Sub Type: Proximity Switch
• Kit Contents: Board
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Sensitivity: -
• Sensing Range: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-6403; STEVAL-IFS006V1

ST7LITEUS2, ST7LITEUS5
10.3.4
●
While the ADC is on, these two phases are continuously repeated.
At the end of each conversion, the sample capacitor is kept loaded with the previous
measurement load. The advantage of this behavior is that it minimizes the current
consumption on the analog pin in case of single input channel measurement.
A/D conversion
The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the “I/O
ports” chapter. Using these pins as analog inputs does not affect the ability of the port to be
read as a logic input.
In the ADCCSR register, select the CS[2:0] bits to assign the analog channel to convert.
ADC conversion mode
In the ADCCSR register, set the ADON bit to enable the A/D converter and to start the
conversion. From this time on, the ADC performs a continuous conversion of the selected
channel. When a conversion is complete:
●
●
A read to the ADCDRH resets the EOC bit.
To read the 10 bits, perform the following steps:
1.
2.
3.
To read only 8 bits, perform the following steps:
1.
1.
Low power modes
The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed and between single shot conversions.
Table 31.
Wait
Halt
cycles) and the C
the optimum analog to digital conversion accuracy.
The total conversion time:
t
The EOC bit is set by hardware.
The result is in the ADCDR registers.
Poll EOC bit
Read ADCDRL
Read ADCDRH. This clears EOC automatically.
Poll EOC bit
Read ADCDRH. This clears EOC automatically.
CONV =
Mode
t
Effect of low power modes
SAMPLE
No effect on A/D converter
A/D converter disabled.
After wakeup from Halt mode, the A/D converter requires a stabilization time
t
can be performed.
STAB
+ t
ADC
HOLD
(see
sample capacitor is disconnected from the analog input pin to get
Section 12: Electrical
characteristics) before accurate conversions
Description
On-chip peripherals
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