STEVAL-IFS006V1 STMicroelectronics, STEVAL-IFS006V1 Datasheet - Page 40
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STEVAL-IFS006V1
Manufacturer Part Number
STEVAL-IFS006V1
Description
BOARD EVAL 8BIT MICRO + TDE1708
Manufacturer
STMicroelectronics
Datasheets
1.TDE1708DFT.pdf
(14 pages)
2.STEVAL-IFS006V1.pdf
(136 pages)
3.STEVAL-IFS006V1.pdf
(4 pages)
Specifications of STEVAL-IFS006V1
Design Resources
STEVAL-IFS006V1 Bill of Material
Sensor Type
Proximity
Interface
I²C
Voltage - Supply
6 V ~ 48 V
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
ST7FLITEUS5, TDE1708
Processor To Be Evaluated
ST7LITEUS5
Data Bus Width
8 bit
Operating Supply Voltage
6 V to 48 V
Silicon Manufacturer
ST Micro
Silicon Core Number
TDE1708DFT
Kit Application Type
Sensing - Touch / Proximity
Application Sub Type
Proximity Switch
Kit Contents
Board
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Sensitivity
-
Sensing Range
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-6403
STEVAL-IFS006V1
STEVAL-IFS006V1
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Interrupts
7.2
Caution:
7.3
Note:
40/136
External interrupts
External interrupt vectors can be loaded into the PC register if the corresponding external
interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the
Halt low power mode.
The external interrupt polarity is selected through the miscellaneous register or interrupt
register (if available).
An external interrupt triggered on edge will be latched and the interrupt request
automatically cleared upon entering the interrupt service routine.
The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies
to the ei source. In case of a NANDed source (as described in the I/O ports section), a low
level on an I/O pin, configured as input with interrupt, masks the interrupt request even in
case of rising-edge sensitivity.
Peripheral interrupts
Different peripheral interrupt flags in the status register are able to cause an interrupt when
they are active if both:
●
●
If any of these two conditions is false, the interrupt is latched and thus remains pending.
Clearing an interrupt request is done by:
●
●
The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for
being enabled) will therefore be lost if the clear sequence is executed.
Figure 14. Interrupt processing flowchart
The I bit of the CC register is cleared.
The corresponding enable bit is set in the control register.
Writing “0” to the corresponding bit in the status register or
Access to the status register while the flag is set followed by a read or write of an
associated register.
FROM RESET
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
FETCH NEXT INSTRUCTION
N
I BIT SET?
IRET?
Y
Y
N
LOAD PC FROM INTERRUPT VECTOR
N
ST7LITEUS2, ST7LITEUS5
STACK PC, X, A, CC
INTERRUPT
PENDING?
SET I BIT
Y