STEVAL-IFS006V1 STMicroelectronics, STEVAL-IFS006V1 Datasheet - Page 52
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STEVAL-IFS006V1
Manufacturer Part Number
STEVAL-IFS006V1
Description
BOARD EVAL 8BIT MICRO + TDE1708
Manufacturer
STMicroelectronics
Datasheets
1.TDE1708DFT.pdf
(14 pages)
2.STEVAL-IFS006V1.pdf
(136 pages)
3.STEVAL-IFS006V1.pdf
(4 pages)
Specifications of STEVAL-IFS006V1
Design Resources
STEVAL-IFS006V1 Bill of Material
Sensor Type
Proximity
Interface
I²C
Voltage - Supply
6 V ~ 48 V
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
ST7FLITEUS5, TDE1708
Processor To Be Evaluated
ST7LITEUS5
Data Bus Width
8 bit
Operating Supply Voltage
6 V to 48 V
Silicon Manufacturer
ST Micro
Silicon Core Number
TDE1708DFT
Kit Application Type
Sensing - Touch / Proximity
Application Sub Type
Proximity Switch
Kit Contents
Board
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Sensitivity
-
Sensing Range
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-6403
STEVAL-IFS006V1
STEVAL-IFS006V1
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Power saving modes
8.4.2
52/136
Figure 22. Active-halt mode flowchart
1. This delay occurs only if the MCU exits Active-halt mode by means of a reset.
2. Peripherals clocked with an external clock source can still be active.
3. Only the Lite Timer RTC and AT Timer interrupts can exit the MCU from Active-halt mode.
4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
Halt mode
The Halt mode is the lowest power consumption mode of the MCU. It is entered by
executing the ‘HALT’ instruction when Active-halt mode is disabled.
The MCU can exit Halt mode on reception of either a specific interrupt (see
Interrupt
the main oscillator is immediately turned on and the 64 CPU cycle delay is used to stabilize
it. After the start up delay, the CPU resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see
When entering Halt mode, the I bit in the CC register is forced to 0 to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes immediately.
In Halt mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
ones which get their clock supply from another clock generator (such as an external or
auxiliary oscillator).
The compatibility of watchdog operation with Halt mode is configured by the “WDGHALT”
option bit of the option byte. The HALT instruction when executed while the watchdog
system is enabled, can generate a watchdog reset (see
details).
during the interrupt routine and cleared when the CC register is popped.
mapping) or a reset. When exiting Halt mode by means of a reset or an interrupt,
HALT INSTRUCTION
(Active-halt enabled)
N
INTERRUPT
Y
3)
OR SERVICE INTERRUPT
FETCH RESET VECTOR
64 CPU CLOCK CYCLE
OSCILLATOR
PERIPHERALS
CPU
OSCILLATOR
PERIPHERALS
CPU
OSCILLATOR
PERIPHERALS
CPU
I BIT
I BIT
I BITS
N
DELAY
RESET
Y
Figure
2)
2)
OFF
OFF
OFF
24).
ON
ON
ON
X
ON
ON
ON
X
0
4)
4)
Section 14.1: Option bytes
ST7LITEUS2, ST7LITEUS5
Table 9:
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