STM3210C-EVAL STMicroelectronics, STM3210C-EVAL Datasheet - Page 9

• Manufacturer Part Number: STM3210C-EVAL
• Description: EVAL BOARD FOR STM32F107VCT
• Manufacturer: STMicroelectronics
• Type: MCUr

Specifications of STM3210C-EVAL

• Contents: Fully Assembled Evaluation Board
• Processor To Be Evaluated: STM32F107VCT
• Processor Series: STM32
• Interface Type: RS-232, USB, I2C, JTAG
• Operating Supply Voltage: 5 V
• For Use With/related Products: STM32F107
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8924

UM0600
2.2
2.3
2.4
Boot option
The STM3210C-EVAL board is able to boot from:
The boot option is configured by setting switches SW1 (BOOT1) and SW2 (BOOT0).
The BOOT0 can be configured also via the RS-232 connector CN6 when JP18 is fitted.
Table 3.
Clock source
Two clock sources are available on the STM3210C-EVAL evaluation board for
STM32F107VCT and RTC is embedded.
Reset source
The reset signal of the STM3210C-EVAL board is active low and the reset sources include:
Table 4.
SW1
and
SW2
JP20
Switch
Jumper
Embedded user Flash
System memory with boot loader for ISP
Embedded SRAM for debugging
X2, 32 kHz crystal for embedded RTC.
X3, 25 MHz crystal with socket for an STM32F107VCT microcontroller, it can be
removed from the socket when an internal RC clock is used.
Reset button, B1
Debugging tools from JTAG connector CN13 and trace connector CN12
Daughterboard from CN9
RS-232 connector CN6 for ISP when JP19 is fitted.
STM3210C-EVAL boots from User Flash when SW2 is set as shown to
the right. SW1 setting does not matter in this configuration. (Default)
STM3210C-EVAL boots from System Memory when SW1 and SW2 are
set as shown:
STM3210C-EVAL boots from Embedded SRAM when SW1 and SW2
are set as shown:
Enables reset of the STM32F107VCT embedded JTAG TAP controller each time a system
reset occurs. JP20 connects the TRST signal from the JTAG connection with the system
reset signal RESET#. Default setting: Not fitted.
Boot related switches
Reset related jumper
Doc ID 15082 Rev 3
Boot from
Description
Hardware layout and configuration
0 <
0 <
0 <
Configuration
> 1
> 1
> 1
SW2
SW1
SW1
SW2
SW2
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