DV164136 Microchip Technology, DV164136 Datasheet - Page 289

• Manufacturer Part Number: DV164136
• Description: DEVELOPMENT KIT FOR PIC18
• Manufacturer: Microchip Technology
• Series: PIC®r
• Type: MCUr

Specifications of DV164136

• Contents: Board, Cables, CDs, PICkit™ 3 Programmer, Power Supply
• Processor To Be Evaluated: PIC18F8722, PIC18F87J11
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3.3 V, 5 V
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18F8xxx
• Kit Contents: PIC18 Exp Brd PICkit 3 Cable CD PSU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PIC18F8722, PIC18F87J11
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

20.3.2
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTAx<5>) or the Continuous Receive
Enable bit, CREN (RCSTAx<4>). Data is sampled on
the RXx pin on the falling edge of the clock.
If enable bit, SREN, is set, only a single word is
received. If enable bit, CREN, is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
To set up a Synchronous Master Reception:
1.
2.
FIGURE 20-13:
© 2009 Microchip Technology Inc.
RC6/TX1/CK1 pin
RC6/TX1/CK1 pin
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. This example is equally applicable to EUSART2
Initialize the SPBRGHx:SPBRGx registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud rate.
Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
RC7/RX1/DT1
(TXCKP = 0)
(TXCKP = 1)
(Interrupt)
(RG1/TX2/CK2 and RG2/RX2/DT2).
RC1IF bit
bit SREN
SREN bit
CREN bit
RCREG1
Write to
EUSART SYNCHRONOUS
MASTER RECEPTION
Read
pin
Q2
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
‘0’
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
bit 0
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 1
bit 2
bit 3
PIC18F87J11 FAMILY
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
11. If using interrupts, ensure that the GIE and PEIE bits
Ensure bits, CREN and SREN, are clear.
If interrupts are desired, set enable bit, RCxIE.
If 9-bit reception is desired, set bit, RX9.
If a single reception is required, set bit, SREN.
For continuous reception, set bit, CREN.
Interrupt flag bit, RCxIF, will be set when recep-
tion is complete and an interrupt will be generated
if the enable bit, RCxIE, was set.
Read the RCSTAx register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREGx register.
bit CREN.
in the INTCON register (INTCON<7:6>) are set.
bit 4
bit 5
bit 6
bit 7
DS39778D-page 289
Q1 Q2 Q3 Q4
‘0’