DV164136 Microchip Technology, DV164136 Datasheet - Page 323

• Manufacturer Part Number: DV164136
• Description: DEVELOPMENT KIT FOR PIC18
• Manufacturer: Microchip Technology
• Series: PIC®r
• Type: MCUr

Specifications of DV164136

• Contents: Board, Cables, CDs, PICkit™ 3 Programmer, Power Supply
• Processor To Be Evaluated: PIC18F8722, PIC18F87J11
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3.3 V, 5 V
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18F8xxx
• Kit Contents: PIC18 Exp Brd PICkit 3 Cable CD PSU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PIC18F8722, PIC18F87J11
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

24.2
For PIC18F87J11 Family devices, the WDT is driven by
the INTRC oscillator. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period
is 4 ms and has the same stability as the INTRC
oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexor, controlled by the WDTPS bits
in Configuration Register 2H. Available periods range
from about 4 ms to 135 seconds (2.25 minutes
depending on voltage, temperature and WDT post-
scaler). The WDT and postscaler are cleared whenever
a SLEEP or CLRWDT instruction is executed, or a clock
failure (primary or Timer1 oscillator) has occurred.
FIGURE 24-1:
© 2009 Microchip Technology Inc.
WDTPS3:WDTPS0
All Device Resets
INTRC Oscillator
Watchdog Timer (WDT)
SWDTEN
CLRWDT
Sleep
WDT BLOCK DIAGRAM
Enable WDT
WDT Counter
÷128
INTRC Control
4
Programmable Postscaler
1:1 to 1:32,768
PIC18F87J11 FAMILY
24.2.1
The WDTCON register (Register 24-9) is a readable
and writable register. The SWDTEN bit enables or dis-
ables WDT operation. This allows software to override
the WDTEN Configuration bit and enable the WDT only
if it has been disabled by the Configuration bit.
The ADSHR bit selects which SFRs are currently
selected and accessible. See Section 5.3.4.1 “Shared
Address SFRs” for additional details.
The LVDSTAT is a read-only status bit which is continu-
ously updated and provides information about the current
level of V
voltage regulator is enabled.
Note 1: The CLRWDT and SLEEP instructions
2: When a CLRWDT instruction is executed,
DDCORE
WDT
CONTROL REGISTER
clear the WDT and postscaler counts
when executed.
the postscaler count will be cleared.
Reset
. This bit is only valid when the on-chip
DS39778D-page 323
Wake-up from
Power-Managed
Modes
WDT
Reset