C8051F800DK Silicon Laboratories Inc, C8051F800DK Datasheet - Page 126
![KIT DEV C8051F800](/photos/28/94/289400/mcudevkit_sml.jpg)
C8051F800DK
Manufacturer Part Number
C8051F800DK
Description
KIT DEV C8051F800
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F800DK
Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
C8051F800
Data Bus Width
16 bit
Interface Type
USB
Operating Supply Voltage
7 V to 15 V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F8xx
Lead Free Status / Rohs Status
Supplier Unconfirmed
Other names
336-1797
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C8051F80x-83x
SFR Definition 21.1. VDM0CN: V
SFR Address = 0xFF
21.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Section “7. Electrical Characteristics”
on page 39 for complete RST pin specifications. The PINRSF flag (RSTSRC.0) is set on exit from an exter-
nal reset.
21.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than the MCD timeout, the one-shot will time out and generate a reset.
After a MCD reset, the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset source; oth-
erwise, this bit reads 0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 dis-
ables it. The state of the RST pin is unaffected by this reset.
126
Name
Reset
5:0
Bit
Type
7
6
Bit
VDDSTAT
VDMEN
Unused
VDMEN
Name
Varies
R/W
7
VDDSTAT
V
This bit turns the V
tem resets until it is also selected as a reset source in register RSTSRC (SFR Def-
inition 21.2). Selecting the V
may generate a system reset. In systems where this reset would be undesirable, a
delay should be introduced between enabling the V
reset source. After a power-on reset, the VDD monitor is enabled, and this bit will
read 1. The state of this bit is sticky through any other reset source.
0: V
1: V
V
This bit indicates the current power supply status (V
0: V
1: V
Read = Varies; Write = Don’t care.
Varies
DD
DD
R
6
DD
DD
DD
DD
Monitor Enable.
Status.
Monitor Disabled.
Monitor Enabled.
is at or below the V
is above the V
Varies
R
5
DD
DD
DD
monitor circuit on/off. The V
Monitor Control
monitor threshold.
Varies
Rev. 1.0
DD
R
4
DD
monitor threshold.
monitor as a reset source before it has stabilized
Function
Varies
R
3
Varies
DD
R
2
DD
DD
Monitor cannot generate sys-
Monitor and selecting it as a
Monitor output).
Varies
R
1
Varies
R
0
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