C8051F800DK Silicon Laboratories Inc, C8051F800DK Datasheet - Page 155

KIT DEV C8051F800

C8051F800DK

Manufacturer Part Number
C8051F800DK
Description
KIT DEV C8051F800
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F800DK

Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
C8051F800
Data Bus Width
16 bit
Interface Type
USB
Operating Supply Voltage
7 V to 15 V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F8xx
Lead Free Status / Rohs Status
Supplier Unconfirmed
Other names
336-1797
SFR Definition 23.10. P0SKIP: Port 0 Skip
SFR Address = 0xD4
SFR Definition 23.11. P1: Port 1
SFR Address = 0x90; Bit-Addressable
Name
Reset
Name
Reset
Bit
7:0
Bit
7:0
Type
Type
Bit
Bit
P0SKIP[7:0]
P1[7:0]
Name
Name
7
0
7
1
Port 1 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Note: P1.4–P1.7 are not
Port 0 Crossbar Skip Enable Bits.
These bits select Port 0 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P0.n pin is not skipped by the Crossbar.
1: Corresponding P0.n pin is skipped by the Crossbar.
available on 16-pin
packages.
6
0
6
1
Description
5
0
5
1
Rev. 1.0
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
4
0
4
1
P0SKIP[7:0]
P1[7:0]
R/W
R/W
Function
Write
3
0
3
1
C8051F80x-83x
2
0
2
1
0: P1.n Port pin is logic
LOW.
1: P1.n Port pin is logic
HIGH.
1
0
1
1
Read
0
0
0
1
155

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