C8051F800DK Silicon Laboratories Inc, C8051F800DK Datasheet - Page 233

• Manufacturer Part Number: C8051F800DK
• Description: KIT DEV C8051F800
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F800DK

• Contents: Board, Cables, CD, Debugger, Power Supply
• Processor To Be Evaluated: C8051F800
• Data Bus Width: 16 bit
• Interface Type: USB
• Operating Supply Voltage: 7 V to 15 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F8xx
• Lead Free Status / Rohs Status: Supplier Unconfirmed
• Other names: 336-1797

29.3.5.1. 8-bit Pulse Width Modulator Mode
The duty cycle of the PWM output signal in 8-bit PWM mode is varied using the module's PCA0CPLn cap-
ture/compare register. When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the
value in PCA0CPLn, the output on the CEXn pin will be set. When the count value in PCA0L overflows, the
CEXn output will be reset (see Figure 29.8). Also, when the counter/timer low byte (PCA0L) overflows from
0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stored in the module’s capture/compare
high byte (PCA0CPHn) without software intervention. This synchronous update feature allows software to
asynchronously write a new PWM high time, which will then take effect on the following PWM period.
Setting the ECOMn and PWMn bits in the PCA0CPMn register, and setting the CLSEL bits in register
PCA0PWM to 000b enables 8-Bit Pulse Width Modulator mode. If the MATn bit is set to 1, the CCFn flag
for the module will be set each time an 8-bit comparator match (rising edge) occurs. The COVF flag in
PCA0PWM can be used to detect the overflow (falling edge), which will occur every 256 PCA clock cycles.
The duty cycle for 8-Bit PWM Mode is given in Equation 29.2.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Using Equation 29.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is
0.39% (PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
PCA0CPLn
Write to
Reset
PCA0CPHn
A
R
S
E
L
0
Write to
C
O
PCA0PWM
E
V
x
C
O
V
F
E
A
R
1
6
x
C
S
E
L
L
2
0
0
ENB
ENB
1
C
S
E
L
L
1
0
C
L
S
E
L
0
0
W
M
P
1
6
n
0
E
C
O
M
n
PCA0CPMn
C
A
P
P
n
0 0 x 0
Figure 29.8. PCA 8-Bit PWM Mode Diagram
C
N
A
P
n
M
A
T
n
Equation 29.2. 8-Bit PWM Duty Cycle
O
G
T
n
Duty Cycle
P
W
M
n
E
C
C
F
n
x
PCA Timebase
Enable
=
PCA0CPHn
Comparator
PCA0CPLn
Rev. 1.0

-------------------------------------------------- -
PCA0L
256 PCA0CPHn
8-bit
–
256
Overflow
COVF
Match
S
R
SET
CLR

C8051F80x-83x
Q
Q
CEXn
Crossbar
Port I/O
233