C8051F800DK Silicon Laboratories Inc, C8051F800DK Datasheet - Page 139

• Manufacturer Part Number: C8051F800DK
• Description: KIT DEV C8051F800
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F800DK

• Contents: Board, Cables, CD, Debugger, Power Supply
• Processor To Be Evaluated: C8051F800
• Data Bus Width: 16 bit
• Interface Type: USB
• Operating Supply Voltage: 7 V to 15 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F8xx
• Lead Free Status / Rohs Status: Supplier Unconfirmed
• Other names: 336-1797

23.1. Port I/O Modes of Operation
Port pins P0.0–P1.7 use the Port I/O cell shown in Figure 23.2. Each Port I/O cell can be configured by
software for analog I/O or digital I/O using the PnMDIN and PnMDOUT registers. Port pin P2.0 can be con-
figured by software for digital I/O using the P2MDOUT register. On reset, all Port I/O cells default to a high
impedance state with weak pull-ups enabled. Until the crossbar is enabled (XBARE = 1), both the high and
low port I/O drive circuits are explicitly disabled on all crossbar pins.
23.1.1. Port Pins Configured for Analog I/O
Any pins to be used as Comparator or ADC input, Capacitive Sense input, external oscillator input/output,
VREF output, or AGND connection should be configured for analog I/O (PnMDIN.n = 0, Pn.n = 1). When a
pin is configured for analog I/O, its weak pullup, digital driver, and digital receiver are disabled. To prevent
the low port I/o drive circuit from pulling the pin low, a ‘1’ should be written to the corresponding port latch
(Pn.n = 1). Port pins configured for analog I/O will always read back a value of 0 regardless of the actual
voltage on the pin.
Configuring pins as analog I/O saves power and isolates the Port pin from digital interference. Port pins
configured as digital I/O may still be used by analog peripherals; however, this practice is not recom-
mended and may result in measurement errors.
23.1.2. Port Pins Configured For Digital I/O
Any pins to be used by digital peripherals (UART, SPI, SMBus, etc.), external digital event capture func-
tions, or as GPIO should be configured as digital I/O (PnMDIN.n = 1). For digital I/O pins, one of two output
modes (push-pull or open-drain) must be selected using the PnMDOUT registers.
Push-pull outputs (PnMDOUT.n = 1) drive the Port pad to the VDD or GND supply rails based on the out-
put logic value of the Port pin. Open-drain outputs have the high side driver disabled; therefore, they only
drive the Port pad to GND when the output logic value is 0 and become high impedance inputs (both high
and low drivers turned off) when the output logic value is 1.
When a digital I/O cell is placed in the high impedance state, a weak pull-up transistor pulls the Port pad to
the VDD supply voltage to ensure the digital input is at a defined logic state. Weak pull-ups are disabled
when the I/O cell is driven to GND to minimize power consumption and may be globally disabled by setting
WEAKPUD to 1. The user should ensure that digital I/O are always internally or externally pulled or driven
to a valid logic state to minimize power consumption. Port pins configured for digital I/O always read back
the logic state of the Port pad, regardless of the output logic value of the Port pin.
PxMDOUT.x
(1 for push-pull)
(0 for open-drain)
Px.x – Output
Logic Value
(Port Latch or
Crossbar)
PxMDIN.x
(1 for digital)
(0 for analog)
Px.x – Input Logic Value
(Reads 0 when pin is configured as an analog I/O)
WEAKPUD
(Weak Pull-Up Disable)
XBARE
(Crossbar
Enable)
To/From Analog
Peripheral
Figure 23.2. Port I/O Cell Block Diagram
Rev. 1.0
GND
VIO
C8051F80x-83x
VIO
(WEAK)
PORT
PAD
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