C8051F800DK Silicon Laboratories Inc, C8051F800DK Datasheet - Page 197
C8051F800DK
Manufacturer Part Number
C8051F800DK
Description
KIT DEV C8051F800
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F800DK
Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
C8051F800
Data Bus Width
16 bit
Interface Type
USB
Operating Supply Voltage
7 V to 15 V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F8xx
Lead Free Status / Rohs Status
Supplier Unconfirmed
Other names
336-1797
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Table 26.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0)
1100
1000 1
1110
Values Read
0
0
0
0 X
0
0
0 X
0
1
A master START was gener-
ated.
A master data or address byte
was transmitted; NACK
received.
A master data or address byte
was transmitted; ACK
received.
A master data byte was
received; ACK requested.
Current SMbus State
Rev. 1.0
Load slave address + R/W into
SMB0DAT.
Set STA to restart transfer.
Abort transfer.
Load next data byte into
SMB0DAT.
End transfer with STOP.
End transfer with STOP and start
another transfer.
Send repeated START.
Switch to Master Receiver Mode
(clear SI without writing new data
to SMB0DAT).
Acknowledge received byte;
Read SMB0DAT.
Send NACK to indicate last byte,
and send STOP.
Send NACK to indicate last byte,
and send STOP followed by
START.
Send ACK followed by repeated
START.
Send NACK to indicate last byte,
and send repeated START.
Send ACK and switch to Master
Transmitter Mode (write to
SMB0DAT before clearing SI).
Send NACK and switch to Mas-
ter Transmitter Mode (write to
SMB0DAT before clearing SI).
Typical Response Options
C8051F80x-83x
Values to
0
1
0
0
0
1
1
0
0
0
1
1
1
0
0
Write
0 X 1100
0 X
1 X
0 X 1100
1 X
1 X
0 X
0 X 1000
0 1
1 0
1 0
0 1
0 0
0 1
0 0
1000
1100
1100
1110
1110
1110
1110
1110
—
—
—
—
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