HW-V5-ML501-UNI-G Xilinx Inc, HW-V5-ML501-UNI-G Datasheet - Page 22

• Manufacturer Part Number: HW-V5-ML501-UNI-G
• Description: EVALUATION PLATFORM VIRTEX-5
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr
• Type: FPGAr

Specifications of HW-V5-ML501-UNI-G

• Design Resources: ML501 Ref Design User Guide ML501 Schematics
• Contents: ML501 Platform, DVI Adapter and CompactFlash Card
• Silicon Manufacturer: Xilinx
• Features: Programmable System Clock Generator Chip, RS-232 Serial Port
• Silicon Family Name: Virtex-5
• Silicon Core Number: XC5VLX50FFG676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: XC5VLX50FFG676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1508

Chapter 1: ML501 Evaluation Platform
22
Single-Ended Expansion I/O Connectors
Header J6 contains 32 single-ended signal connections to the FPGA I/Os. This permits the
signals on this connector to carry high-speed, single-ended data. All single-ended signals
on connector J6 are matched length traces. The V
3.3V by setting jumper J20.
expansion I/O connector.
Table 1-10: Expansion I/O Single-Ended Connections (J6)
J6 Pin
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
2
4
6
8
Schematic Net Name
www.xilinx.com
Table 1-10
HDR1_10
HDR1_12
HDR1_14
HDR1_16
HDR1_18
HDR1_20
HDR1_22
HDR1_24
HDR1_26
HDR1_28
HDR1_30
HDR1_32
HDR1_34
HDR1_36
HDR1_38
HDR1_40
HDR1_42
HDR1_44
HDR1_46
HDR1_48
HDR1_50
HDR1_52
HDR1_54
HDR1_2
HDR1_4
HDR1_6
HDR1_8
summarizes the single-ended connections on this
CCIO
of these signals can be set to 2.5V or
FPGA Pin
AB25
M22
M21
M26
M25
M24
W25
W26
H23
N24
N26
K20
K21
K26
K25
U24
U25
Y25
L25
L24
P25
P24
T24
T25
J20
J23
J21
UG226 (v1.4) August 24, 2009
ML501 Evaluation Platform
R