HW-V5-ML501-UNI-G Xilinx Inc, HW-V5-ML501-UNI-G Datasheet - Page 29

• Manufacturer Part Number: HW-V5-ML501-UNI-G
• Description: EVALUATION PLATFORM VIRTEX-5
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr
• Type: FPGAr

Specifications of HW-V5-ML501-UNI-G

• Design Resources: ML501 Ref Design User Guide ML501 Schematics
• Contents: ML501 Platform, DVI Adapter and CompactFlash Card
• Silicon Manufacturer: Xilinx
• Features: Programmable System Clock Generator Chip, RS-232 Serial Port
• Silicon Family Name: Virtex-5
• Silicon Core Number: XC5VLX50FFG676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: XC5VLX50FFG676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1508

Table 1-13: Board Connections for PHY Configuration Pins
ML501 Evaluation Platform
UG226 (v1.4) August 24, 2009
Config Pin
CONFIG0
CONFIG1
CONFIG2
CONFIG3
CONFIG4
CONFIG5
CONFIG6
22. USB Controller with Host and Peripheral Ports
R
Connection on
V
LED_DUPLEX
(Set by J40)
CC
V
V
V
V
LED_RX
Ground
Board
CC
CC
CC
CC
2.5V or
2.5V
2.5V
2.5V
2.5V
settings (See
whether the PHY defaults to RGMII mode (pin 2-3) or GMII mode (pin 1-2).
A Cypress CY7C67300 embedded USB host controller provides USB connectivity for the
board. The USB controller supports host and peripheral modes of operation. The USB
controller has two serial interface engines (SIE) that can be used independently. SIE1 is
connected to the USB Host connector (P19). SIE2 is connected only to the USB Peripheral
connector (P17).
The USB controller has an internal microprocessor to assist in processing USB commands.
The firmware for this processor can be stored in its own dedicated IIC EEPROM (U28) or
can be downloaded from a host computer via a peripheral connector. The USB controller's
serial port is connected to J30 through an RS-232 transceiver to assist with debug. Jumper
J50 can be installed to prevent the USB controller from executing firmware stored in the IIC
EEPROM.
PHYADR[2] = 1
ENA_PAUSE = 0
ANEG[3] = 1
ANEG[0] = 1
HWCFG_MODE[2] = 0 or 1
(Set by J40)
DIS_FC = 1
SEL_BDT = 0
Definition and Value
Table
Bit[2]
1-13). These settings can be overwritten via software. Jumper J40 selects
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PHYADR[1] = 1
PHYADR[4] = 0
HWCFG_MODE[1] = 1
INT_POL = 1
ANEG[2] = 1
ENA_XC = 1
DIS_SLEEP = 1
Definition and Value
Bit[1]
PHYADR[0] = 1
PHYADR[3] = 0
ANEG[1] = 1
DIS_125 = 1
HWCFG_MODE[0] = 1
HWCFG_MODE[3] = 1
75/50Ω = 0
Definition and Value
Detailed Description
Bit[0]
29