HW-V5-ML501-UNI-G Xilinx Inc, HW-V5-ML501-UNI-G Datasheet - Page 26

• Manufacturer Part Number: HW-V5-ML501-UNI-G
• Description: EVALUATION PLATFORM VIRTEX-5
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr
• Type: FPGAr

Specifications of HW-V5-ML501-UNI-G

• Design Resources: ML501 Ref Design User Guide ML501 Schematics
• Contents: ML501 Platform, DVI Adapter and CompactFlash Card
• Silicon Manufacturer: Xilinx
• Features: Programmable System Clock Generator Chip, RS-232 Serial Port
• Silicon Family Name: Virtex-5
• Silicon Core Number: XC5VLX50FFG676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: XC5VLX50FFG676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1508

Chapter 1: ML501 Evaluation Platform
26
14. IIC Bus with 8-Kb EEPROM
15. DVI Connector
16. PS/2 Mouse and Keyboard Ports
An IIC EEPROM (STMicroelectronics M24C08) is provided on the board to store non-
volatile data such as an Ethernet MAC address. The EEPROM is located under the
removable LCD and is not visible in
the board. IIC bus pull-up resistors are provided on the board.
The IIC bus is extended to the expansion connector so that the user can add additional IIC
devices and share the IIC controller in the FPGA. If the expansion IIC bus is to be utilized,
the user must have additional IIC pull-up resistors present on the expansion card.
Bidirectional level shifting transistors allow the expansion card to utilize 2.5V to 5V
signaling on IIC.
A DVI connector (P7) is present on the board to support an external video monitor. The
DVI circuitry utilizes a Chrontel CH7301C capable of 1600 X 1200 resolution with 24-bit
color. The video interface chip drives both the digital and analog signals to the DVI
connector. A DVI monitor can be connected to the board directly. A VGA monitor can also
be connected to the board using the supplied DVI-to-VGA adaptor. The Chrontel
CH7301C is controlled by way of the VGA IIC bus.
The DVI connector supports the IIC protocol to allow the board to read the monitor’s
configuration parameters. These parameters can be read by the FPGA using the VGA IIC
bus.
The ML501 Evaluation Platform contains two PS/2 ports: one for a mouse (P5) and the
other for a keyboard (P4). Bidirectional level shifting transistors allow the FPGA's
1.8V I/O to interface with the 5V I/O of the PS/2 ports. The PS/2 ports on the board are
powered directly by the main 5V power jack, which also powers the rest of the board.
Caution!
not overload the AC adapter.
Care must be taken to ensure that the power load of any attached PS/2 devices does
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Figure
1-2. The EEPROM write protect is disabled on
UG226 (v1.4) August 24, 2009
ML501 Evaluation Platform
R