C8051F540-TB Silicon Laboratories Inc, C8051F540-TB Datasheet - Page 18
![BOARD PROTOTYPE W/C8051F540](/photos/9/25/92559/c8051f540-tb_sml.jpg)
C8051F540-TB
Manufacturer Part Number
C8051F540-TB
Description
BOARD PROTOTYPE W/C8051F540
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F540-TB
Contents
Board
Processor To Be Evaluated
C8051F54x
Processor Series
C8051F54x
Interface Type
USB
Operating Supply Voltage
5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F54x
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1672
- Current page: 18 of 274
- Download datasheet (3Mb)
C8051F54x
3. Pin Definitions
18
VREGIN
GNDA
Name
VDDA
C2CK
P2.1/
P3.0/
GND
RST/
VDD
C2D
C2D
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
VIO
‘F540/1/4/5
(32-pin)
Pin
10
32
31
30
29
28
27
26
25
24
—
4
6
5
7
3
2
9
8
1
‘F542/3/6/7
(24-pin)
Table 3.1. Pin Definitions for the C8051F54x
Pin
24
23
22
21
20
19
18
17
16
15
—
—
3
4
5
2
1
8
7
6
D I/O or A In
D I/O or A In
D I/O or A In Port 0.0. See SFR Definition 18.12 for a description.
D I/O or A In Port 0.1
D I/O or A In Port 0.2
D I/O or A In Port 0.3
D I/O or A In Port 0.4
D I/O or A In Port 0.5
D I/O or A In Port 0.6
D I/O or A In Port 0.7
D I/O or A In Port 1.0. See SFR Definition 18.16 for a description.
D I/O or A In Port 1.1.
D I/O or A In Port 1.2.
D I/O
D I/O
D I/O
D I/O
Type
Digital Supply Voltage. Must be connected.
Digital Ground. Must be connected.
Analog Supply Voltage. Must be connected. Connected
internally to VDD on the 24-pin packages.
Analog Ground. Must be connected.
Voltage Regulator Input
Port I/O Supply Voltage. Must be connected.
Device Reset. Open-drain output of internal POR or
V
Clock signal for the C2 Debug Interface.
Port 2.1. See SFR Definition 18.20 for a description.
Bi-directional data signal for the C2 Debug Interface.
Port 3.0. See SFR Definition 18.24 for a description.
Bi-directional data signal for the C2 Debug Interface.
Rev. 1.1
DD
Monitor.
Description
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