C8051F540-TB Silicon Laboratories Inc, C8051F540-TB Datasheet - Page 251
C8051F540-TB
Manufacturer Part Number
C8051F540-TB
Description
BOARD PROTOTYPE W/C8051F540
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F540-TB
Contents
Board
Processor To Be Evaluated
C8051F54x
Processor Series
C8051F54x
Interface Type
USB
Operating Supply Voltage
5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F54x
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1672
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24.2. PCA0 Interrupt Sources
Figure 24.3 shows a diagram of the PCA interrupt tree. There are five independent event flags that can be
used to generate a PCA0 interrupt. They are as follows: the main PCA counter overflow flag (CF), which is
set upon a 16-bit overflow of the PCA0 counter, an intermediate overflow flag (COVF), which can be set on
an overflow from the 8th, 9th, 10th, or 11th bit of the PCA0 counter, and the individual flags for each PCA
channel (CCF0, CCF1, CCF2, CCF3, CCF4, and CCF5), which are set according to the operation mode of
that module. These event flags are always set when the trigger condition occurs. Each of these flags can
be individually selected to generate a PCA0 interrupt, using the corresponding interrupt enable flag (ECF
for CF, ECOV for COVF, and ECCFn for each CCFn). PCA0 interrupts must be globally enabled before any
individual interrupt sources are recognized by the processor. PCA0 interrupts are globally enabled by set-
ting the EA bit and the EPCA0 bit to logic 1.
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
C
D
L
I
W
D
T
E
PCA0MD
W
D
C
L
K
C
P
S
2
000
001
010
011
100
101
C
P
S
1
C
P
S
0
E
C
F
Figure 24.2. PCA Counter/Timer Block Diagram
IDLE
C
F
C
R
PCA0CN
C
C
F
5
C
C
F
4
C
C
F
3
C
C
F
2
C
C
F
1
C
C
F
0
Rev. 1.1
0
1
PCA0L
read
Snapshot
Register
PCA0H
PCA0L
To SFR Bus
To PCA Modules
Overflow
C8051F54x
CF
To PCA Interrupt System
251
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