C8051F540-TB Silicon Laboratories Inc, C8051F540-TB Datasheet - Page 263

BOARD PROTOTYPE W/C8051F540

C8051F540-TB

Manufacturer Part Number
C8051F540-TB
Description
BOARD PROTOTYPE W/C8051F540
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F540-TB

Contents
Board
Processor To Be Evaluated
C8051F54x
Processor Series
C8051F54x
Interface Type
USB
Operating Supply Voltage
5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F54x
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1672
24.5. Register Descriptions for PCA0
Following are detailed descriptions of the special function registers related to the operation of the PCA.
SFR Definition 24.1. PCA0CN: PCA Control
SFR Address = 0xD8; Bit-Addressable; SFR Page = 0x00
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
Name
CCF5
CCF4
CCF3
CCF2
CCF1
CCF0
CR
CF
R/W
CF
7
0
PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000.
When the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the
CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared
by hardware and must be cleared by software.
PCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: PCA Counter/Timer disabled.
1: PCA Counter/Timer enabled.
PCA Module 5 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF5 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
PCA Module 4 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF4 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
PCA Module 3 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF3 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
PCA Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF2 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
PCA Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF1 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
PCA Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF0 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
R/W
CR
6
0
CCF5
R/W
5
0
CCF4
R/W
Rev. 1.1
4
0
Function
CCF3
R/W
3
0
CCF2
R/W
2
0
C8051F54x
CCF1
R/W
1
0
CCF0
R/W
0
0
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