R0E0200F0EMU00 Renesas Electronics America, R0E0200F0EMU00 Datasheet - Page 75

• Manufacturer Part Number: R0E0200F0EMU00
• Description: EMULATOR E200 MAIN BODY-SH7780
• Manufacturer: Renesas Electronics America
• Series: SuperH®r
• Type: In-Circuit Emulatorr

Specifications of R0E0200F0EMU00

• Contents: Emulator Board, Cables, Software and Documentation
• For Use With/related Products: SH7780
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Each measurement condition is also counted when conditions in table 1.6 are generated.
Table 1.6 Performance Measurement Conditions to be Counted
Measurement Condition
No caching due to the
settings of TLB cacheable
bit
Cache-on counting
Branch count
Notes: 1. In the non-realtime trace mode of the AUD trace and memory output trace, normal
• Extension setting of the performance-result storing counter
(b) Displaying the result of performance
Note: If a performance counter overflows as a result of measurement, “********” will be
(c) Initializing the measured result
The 32-bit counter stores the result of performance, and two counters can be used as a 64-bit
counter.
To set a 64-bit counter, check the [Enable] check box in the [Extend counter] group box of the
[Performance Analysis] dialog box for Ch1 and Ch3.
The result of performance is displayed in the [Performance Analysis] window or the
PERFORMANCE_ANALYSIS command in hexadecimal (32 bits).
However, when the extension counter is enabled, it is displayed in hexadecimal (64 bits).
To initialize the measured result, select [Initialize] from the popup menu in the [Performance
Analysis] window or specify INIT with the PERFORMANCE_ANALYSIS command.
2. Since the clock source of the counter is the CPU clock, counting also stops when the
displayed.
counting cannot be performed because the generation state of the stall or the execution
cycle is changed.
clock halts in the sleep mode.
Notes
Counted for accessing the cacheable area.
Accessing the non-cacheable area is counted less than the actual
number of cycles and counts. Accessing the cacheable, X/Y-RAM,
and U-RAM areas is counted more than the actual number of cycles
and counts.
The counter value is incremented by 2. This means that two cycles
are valid for one branch.
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