MCF5232 ETC, MCF5232 Datasheet
MCF5232
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MCF5232 Summary of contents
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Freescale Semiconductor Hardware Specification MCF523x Integrated Microprocessor Hardware Specification 32-bit Embedded Controller Division The MCF523x is a family of highly-integrated 32-bit microcontrollers based on the V2 ColdFire microarchitecture. Featuring channel eTPU, 64 Kbytes of internal SRAM, ...
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Overview • V2 ColdFire core with enhanced multiply-accumulate unit (EMAC) providing 144 Dhrystone 2.1 MIPS @ 150 MHz • eTPU with channels, 6 Kbytes of code memory and 1.5 Kbytes of data memory with Nexus Class 1 ...
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Table 1. MCF523x Family Configurations (continued) Instruction/Data Cache Static RAM (SRAM) Interrupt Controllers (INTC) Edge Port Module (EPORT) External Interface Module (EIM) 4-channel Direct-Memory Access (DMA) SDRAM Controller Fast Ethernet Controller (FEC) Cryptography - Security module for data packets processing ...
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Overview FAST ETHERNET (To/From PADI) CONTROLLER (FEC) (To/From PADI DMA (To/From PADI) DREQ[2:0] DACK[2:0] JTAG_EN NEXUS JTAG TAP eTPU (To/From PADI) Watchdog Timer SKHA FlexCAN RNGA MDHA Cryptography Modules MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 4 (To/From ...
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Features The following section gives a brief overview of this family’s feature set. For more detailed information see the MCF5235 Reference Manual (MCF5235RM). 1.3.1 Feature Overview • Version 2 ColdFire variable-length RISC processor core — Static operation — 32-bit ...
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Overview masters (e.g., DMA, FEC) • Fast Ethernet Controller (FEC) — 10 BaseT capability, half duplex or full duplex — 100 BaseT capability, half duplex or full duplex — On-chip transmit and receive FIFOs — Built-in dedicated DMA controller — ...
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Fully compatible with industry-standard I — Master or slave modes support multiple masters — Automatic interrupt generation with programmable level • Queued Serial Peripheral Interface (QSPI) — Full-duplex, three-wire synchronous transfers — four chip selects available — ...
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... DMA channels and the eTPU (1) • External Bus Interface — Glueless connections to external memory devices (e.g., SRAM, Flash, ROM, etc.) — SDRAM controller supports 8-, 16-, and 32-bit wide memory devices — Support for n-1-1-1 burst fetches from page mode Flash — ...
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... EXTAL — — XTAL — — CLKOUT — — CLKMOD[1:0] — — RCON — — MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor NOTE NOTE MCF5232 MCF5232 1 160 QFP MAPBGA Reset — — Clock — M14 — — ...
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... DACK2 TIP PBUSCTL0 DREQ0 CS[7:4] PCS[7:4] — CS[3:2] PCS[3:2] SD_CS[1:0] CS1 PCS1 — CS0 — — MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 10 MCF5232 MCF5232 1 160 196 QFP MAPBGA — O 126, 125, B11, C11, 124 D11 — O 123:115, A12, B12, 112:106, C12, A13, 102:98 ...
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... ETXD[3:0] TPUCH[15:0] — — TCRCLK PETPU2 — UTPUODIS PETPU1 — LTPUODIS PETPU0 — EMDIO PFECI2C2 I2C_SDA MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor MCF5232 MCF5232 1 160 196 QFP MAPBGA SDRAM Controller — K13 — K12 — K11 — ...
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... QSPI_CLK PQSPI2 I2C_SCL QSPI_DIN PQSPI1 I2C_SDA QSPI_DOUT PQSPI0 — U2TXD PUARTH1 CAN1TX U2RXD PUARTH0 CAN1RX U1CTS PUARTL7 U2CTS MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 12 MCF5232 MCF5232 1 160 196 QFP MAPBGA U2TXD O — — — I — — — I — — — I — ...
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... TMS DSI — TDI DSO — TDO JTAG_EN — — DDATA[3:0] — — PST[3:0] — — MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor MCF5232 MCF5232 1 160 196 QFP MAPBGA — O — — O 135 — I 136 — I — — O — ...
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... Chip Configuration Mode—Device Operating Options • Chip operating mode: — Master mode • Boot device/size: — External device boot – 32-bit – 16-bit (Default) MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 14 MCF5232 MCF5232 1 160 196 QFP MAPBGA Test — — I — ...
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Output pad strength: — Partial drive strength (Default) — Full drive strength • Clock mode: — Normal PLL with external crystal — Normal PLL with external clock — 1:1 PLL Mode — External oscillator mode (no PLL) ...
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Modes of Operation Table 3. Configuration Pin Descriptions (continued) Chip Configuration Pin D25, D24 Select chip select / address line JTAG_EN Selects BDM or JTAG mode 3.2 Low Power Modes The following features are available to support applications which require ...
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WAIT Mode WAIT mode is intended to be used to stop only the CPU core and memory clocks until a wakeup event is detected. In this mode, peripherals may be programmed to continue operating and can generate interrupts, which ...
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Design Recommendations 4.2 Power Supply 33 µF, .1 µF and .01 µF across each power supply • 4.3 Decoupling • Place the decoupling caps as close to the pins as possible, but they can be outside the footprint of the ...
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Table 4. Synchronous DRAM Signal Connections Signal SD_SRAS Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be latched by the SDRAM. SD_SRAS should be connected to the corresponding SDRAM SD_SRAS. Do not confuse SD_SRAS ...
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Design Recommendations Table 5. Generic Address Multiplexing Scheme (continued) Address Pin Row Address Column Address The following tables provide a more comprehensive, step-by-step way to determine the correct address line connections for interfacing the MCF523x ...
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Table 9. MCF523x to SDRAM Interface (8-Bit Port,12-Column Address Lines) MCF523x A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column ...
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Design Recommendations Table 14. MCF523x to SDRAM Interface (16-Bit Port, 11-Column Address Lines) MCF523x A16 A15 A14 A13 A12 A11 A10 A9 A18 A20 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row ...
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Table 19. MCF523x to SDRAM Interface (32-Bit Port, 10-Column Address Lines) MCF523x A15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column ...
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Design Recommendations Transmit clock Transmit enable Transmit data Transmit error Collision Carrier sense Receive clock Receive enable Receive data Receive error Management channel clock Management channel serial data The serial mode interface operates in what is generally referred to as ...
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FlexCAN The FlexCAN module interface to the CAN bus is composed of 2 pins: CANTX and CANRX, which are the serial transmitted data and the serial received data. The use of an external CAN transceiver to interface to the ...
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... Mechanicals/Pinouts and Part Numbers 5.1 Pinout—196 MAPBGA Figure 2 shows a pinout of the MCF5232CVMxxx package VSS TPUCH6 TPUCH3 TPUCH2 A TPUCH8 TPUCH7 TPUCH4 TPUCH0 B C TPUCH10 TPUCH9 TPUCH5 TPUCH1 QSPI_CLK D TPUCH13 TPUCH12 TPUCH11 NC E TPUCH14 TPUCH15 TCRCLK DT0IN U0TXD U0RXD U0CTS DT0OUT ...
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... Package Dimensions—196 MAPBGA Figure 3 shows MCF5232CVMxxx package dimensions Laser mark for pin 1 Y identification in this area E 0. 13X 3 b 196X View M-m 0. 0.10 Z Figure 3. 196 MAPBGA Package Dimensions (Case No. 1128A-01) MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 ...
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Mechanicals/Pinouts and Part Numbers 5.2.1 Pinout—256 MAPBGA Figure 4 through Figure 6 MCF5235CVMxxx packages VSS TPUCH6 TPUCH4 TPUCH2 TPUCH17 TPUCH1 B TPUCH8 TPUCH7 TPUCH5 TPUCH3 TPUCH18 TPUCH19 TPUCH16 C TPUCH10 TPUCH9 TPUCH25 TPUCH24 TPUCH22 TPUCH20 ...
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VSS TPUCH6 TPUCH4 TPUCH2 A TPUCH8 TPUCH7 TPUCH5 TPUCH3 B C TPUCH10 TPUCH9 ERXD1 ERXD0 D TPUCH12 TPUCH11 ERXD3 ERXD2 E TPUCH14 TPUCH13 ERXCLK ERXDV TCRCLK TPUCH15 ECOL ECRS F U0CTS U0RXD DT0OUT DT0IN G VDD ...
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Mechanicals/Pinouts and Part Numbers VSS TPUCH6 TPUCH4 TPUCH2 A B TPUCH8 TPUCH7 TPUCH5 TPUCH3 TPUCH25/ TPUCH24/ C TPUCH10 TPUCH9 ERXD1 ERXD0 TPUCH27/ TPUCH26/ D TPUCH12 TPUCH11 ERXD3 ERXD2 TPUCH29/ TPUCH2/ E TPUCH14 TPUCH13 ERXCLK ERXDV TPUCH31/ ...
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Package Dimensions—256 MAPBGA Figure 7 shows MCF5235CVMxxx, MCF5234CVMxxx, and MCF5233CVMxx package dimensions LASER MARK FOR PIN A1 IDENTIFICATION IN THIS AREA E 0.20 15X ...
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... Mechanicals/Pinouts and Part Numbers 5.3 Pinout—160 QFP Figure 8 shows a pinout of the MCF5232CABxxx package. OVDD 1 TPUCH8 2 TPUCH9 3 TPUCH10 4 TPUCH11 5 TPUCH12 6 TPUCH13 7 VSS 8 OVDD 9 TPUCH14 10 TPUCH15 11 TCRCLK 12 U0RXD 13 U0TXD 14 VDD 15 VSS 16 OVDD 17 TEST 18 CLKMOD1 19 CLKMOD0 20 D31 21 D30 22 D29 23 D28 24 VSS 25 D27 26 D26 27 28 ...
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... Package Dimensions—160 QFP Figure 9 shows MCF5232CAB80 package dimensions. Y –A– 0.20 (0.008) 0.20 (0.008) 0.20 (0.008 –H– –C– H 0.110 (0.004) DETAIL C MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor L –B– B DETAIL DETAIL C – ...
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... Preliminary Electrical Characteristics 5.5 Ordering Information Freescale Part Number MCF5232CAB80 MCF5232 RISC Microprocessor, 160 QFP MCF5232CVM100 MCF5232 RISC Microprocessor, 196 MAPBGA MCF5232CVM150 MCF5232 RISC Microprocessor, 196 MAPBGA MCF5233CVM100 MCF5233 RISC Microprocessor, 256 MAPBGA MCF5233CVM150 MCF5233 RISC Microprocessor, 256 MAPBGA MCF5234CVM100 MCF5234 RISC Microprocessor, 256 MAPBGA ...
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Rating Instantaneous Maximum Current Single pin limit (applies to all pins) Operating Temperature Range (Packaged) Storage Temperature Range NOTES: 1 Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum Ratings are stress ratings only, and functional operation at ...
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Preliminary Electrical Characteristics NOTES: θ and Ψ 1 parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale JMA jt recommends the use of θ and power dissipation specifications in the system design to prevent device junction ...
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P = Power Dissipation on Input and Output Pins — User Determined I/O For most applications P I/O and T ( neglected) is: J I/O Solving equations 1 and 2 for K gives where K ...
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Preliminary Electrical Characteristics Characteristic 4 Load Capacitance Low drive strength High drive strength 5 Core Operating Supply Current Master Mode Pad Operating Supply Current Master Mode Low Power Modes Injection Current V =V – 0.3 ...
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Table 29. HiP7 PLLMRFM Electrical Specifications Num Characteristic 5 Crystal Start-up Time 6 EXTAL Input High Voltage 7 Crystal Mode All other modes (Dual Controller (1:1), Bypass, External) 7 EXTAL Input Low Voltage 7 Crystal Mode All other modes (Dual ...
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Preliminary Electrical Characteristics 8 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). 9 Assuming a reference is available at power up, lock time ...
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Timings listed in Table 30 are shown in * The timings are also valid for inputs sampled on the negative clock edge. CLKOUT(75MHz) Input Setup And Hold Input Rise Time Input Fall Time CLKOUT B4 Inputs Figure 10. General Input ...
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Preliminary Electrical Characteristics Table 31. External Bus Output Timing Specifications (continued) Name Characteristic B8 CLKOUT high to address (A[23:0]) and control (TS, TSIZ[1:0], TIP, R/W) valid B9 CLKOUT high to address (A[23:0]) and control (TS, TSIZ[1:0], TIP, R/W) invalid B11 ...
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S0 CLKOUT B6a CSn B8 A[23:0] TSIZ[1: TIP B8 B6c OE (H) R/W B6b BS[3:0] D[31:0] (H) TA TEA (H) Figure 11. Read/Write (Internally Terminated) SRAM Bus Timing MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor ...
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Preliminary Electrical Characteristics Figure 12 shows a bus cycle terminated by TA showing timings listed in CLKOUT B6a CSn B8 A[23:0] TSIZ[1: TIP B6c OE (H) R/W B6b BS[3:0] D[31:0] TA TEA (H) Figure 12. SRAM Read ...
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CLKOUT B6a CSn B8 A[23:0] TSIZ[1: TIP B6c OE R/W (H) B6b BS[3:0] D[31:0] TA (H) TEA Figure 13. SRAM Read Bus Cycle Terminated by TEA Figure 14 shows an SDRAM read cycle. MCF523x Integrated Microprocessor Hardware ...
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Preliminary Electrical Characteristics SD_CKE D1 A[23:0] Row D2 D4 RAS 1 CAS SDWE D[31:0] D2 RAS[1:0] D2 CAS[3:0] ACTV NOP 1 DACR[CASL NUM D1 CLKOUT high to SDRAM address valid D2 CLKOUT high to SDRAM ...
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SD_CKE D1 A[23:0] Row D2 SD_SRAS 1 SD_SCAS SD_WE D7 D[31:0] D2 RAS[1:0] D2 CAS[3:0] ACTV 1 DACR[CASL 6.7 General Purpose I/O Timing NUM Characteristic G1 CLKOUT High to GPIO Output Valid G2 CLKOUT High to GPIO ...
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Preliminary Electrical Characteristics GPIO Outputs 6.8 Reset and Configuration Override Timing Table 34. Reset and Configuration Override Timing NUM Characteristic R1 RESET Input valid to CLKOUT High R2 CLKOUT High to RESET Input invalid 2 R3 RESET Input valid Time ...
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CLKOUT RESET RSTOUT Configuration Overrides*: (RCON, Override pins]) Figure 17. RESET and Configuration Override Timing * Refer to the Coldfire Integration Module (CIM) section for more information Input/Output Timing Specifications Table 35 lists specifications for the ...
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Preliminary Electrical Characteristics 2 Table 36 Output Timing Specifications between I2C_SCL and I2C_SDA Num 1 I7 Data setup time 1 I8 Start condition setup time (for repeated start condition only Stop condition setup time NOTES: 1 ...
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Num M1 ERXD[3:0], ERXDV, ERXER to ERXCLK setup M2 ERXCLK to ERXD[3:0], ERXDV, ERXER hold M3 ERXCLK pulse width high M4 ERXCLK pulse width low Figure 19 shows MII receive signal timings listed in ERXCLK (input) ERXD[3:0] (inputs) ERXDV ERXER ...
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Preliminary Electrical Characteristics Figure 20 shows MII transmit signal timings listed in ETXCLK (input) ETXD[3:0] (outputs) ETXEN ETXER Figure 20. MII Transmit Signal Timing Diagram 6.10.3 MII Async Inputs Signal Timing (ECRS and ECOL) Table 39 lists MII asynchronous inputs ...
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Figure 22 shows MII serial management channel timings listed in EMDC (output) EMDIO (output) EMDIO (input) Figure 22. MII Serial Management Channel Timing Diagram 6.11 32-Bit Timer Module AC Timing Specifications Table 41 lists timer module AC timings. Table 41. ...
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Preliminary Electrical Characteristics The values in Table 42 correspond to QS1 QSPI_CS[1:0] QSPI_CLK QSPI_DOUT QS3 QSPI_DIN 6.13 JTAG and Boundary Scan Timing Num Characteristics J1 TCLK Frequency of Operation J2 TCLK Cycle Period J3 TCLK Clock Pulse Width J4 TCLK ...
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TCLK (input) TCLK V Data Inputs Data Outputs Data Outputs Data Outputs MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Figure 24. Test Clock Input Timing Figure ...
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Preliminary Electrical Characteristics TCLK V IL TDI TMS TDO TDO TDO TCLK TRST 6.14 Debug AC Timing Specifications Table 44 lists specifications for the debug AC timing parameters shown in Num DE0 PSTCLK cycle time DE1 PST valid to PSTCLK ...
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Num 1 DE5 DSCLK high to DSO invalid DE6 BKPT input data setup time to CLKOUT Rise DE7 CLKOUT high to BKPT high Z NOTES: 1 DSCLK and DSI are synchronized internally measured from the synchronized DSCLK input ...
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Documentation 7 Documentation Table 46 lists the documents that provide a complete description of the MCF523x and their development support tools. Documentation is available from a local Freescale distributor, a Freescale semiconductor sales office, the Freescale Literature Distribution Center, or ...
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THIS PAGE INTENTIONALLY LEFT BLANK MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 59 ...
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HOW TO REACH US: USA/Europe/Locations not listed: Freescale Semiconductor Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 Japan: Freescale Semiconductor Japan Ltd. Technical Information Center 3-20-1, Minami-Azabu, Minato-ku Tokyo 106-8573, Japan 81-3-3440-3569 Asia/Pacific: Freescale Semiconductor H.K. Ltd. ...