IC MCU AVR32 128KB FLASH 144LQFP

AT32UC3A0128-ALUT

Manufacturer Part NumberAT32UC3A0128-ALUT
DescriptionIC MCU AVR32 128KB FLASH 144LQFP
ManufacturerAtmel
SeriesAVR®32 UC3
AT32UC3A0128-ALUT datasheets
 


Specifications of AT32UC3A0128-ALUT

Core ProcessorAVRCore Size32-Bit
Speed66MHzConnectivityEBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o109
Program Memory Size128KB (128K x 8)Program Memory TypeFLASH
Ram Size32K x 8Voltage - Supply (vcc/vdd)1.65 V ~ 1.95 V
Data ConvertersA/D 8x10bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case144-LQFP
Processor SeriesAT32UC3xCoreAVR32
Data Bus Width32 bitData Ram Size32 KB
Interface Type2-Wire, RS-485, SPI, USARTMaximum Clock Frequency66 MHz
Number Of Programmable I/os69Number Of Timers3
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
3rd Party Development ToolsEWAVR32, EWAVR32-BL, KSK-EVK1100-PLDevelopment Tools By SupplierATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature- 40 CController Family/seriesAT32UC3A
No. Of I/o's109Ram Memory Size32KB
Cpu Speed66MHzNo. Of Timers1
Rohs CompliantYesFor Use WithATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
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Table 9-3.
Reg #
92
93
94
95
96
97
98
99
100
101
102
103-191
192-255
9.4
Exceptions and Interrupts
AVR32UC incorporates a powerful exception handling scheme. The different exception sources,
like Illegal Op-code and external interrupt requests, have different priority levels, ensuring a well-
defined behavior when multiple exceptions are received simultaneously. Additionally, pending
exceptions of a higher priority class may preempt handling of ongoing exceptions of a lower pri-
ority class.
When an event occurs, the execution of the instruction stream is halted, and execution control is
passed to an event handler at an address specified in
dlers are placed sequentially in the code space starting at the address specified by EVBA, with
four bytes between each handler. This gives ample space for a jump instruction to be placed
there, jumping to the event routine itself. A few critical handlers have larger spacing between
them, allowing the entire event routine to be placed directly at the address specified by the
EVBA-relative offset generated by hardware. All external interrupt sources have autovectored
interrupt service routine (ISR) addresses. This allows the interrupt controller to directly specify
the ISR address as an address relative to EVBA. The autovector offset has 14 address bits, giv-
ing an offset of maximum 16384 bytes. The target address of the event handler is calculated as
(EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception
code segments must be set up appropriately. The same mechanisms are used to service all dif-
ferent types of events, including external interrupt requests, yielding a uniform event handling
scheme.
An interrupt controller does the priority handling of the external interrupts and provides the
autovector offset to the CPU.
9.4.1
System stack issues
Event handling in AVR32 UC uses the system stack pointed to by the system stack pointer,
SP_SYS, for pushing and popping R8-R12, LR, status register and return address. Since event
code may be timing-critical, SP_SYS should point to memory addresses in the IRAM section,
since the timing of accesses to this memory section is both fast and deterministic.
32058J–AVR32–04/11
System Registers (Continued)
Address
Name
Function
368
MPUPSR4
MPU Privilege Select Register region 4
372
MPUPSR5
MPU Privilege Select Register region 5
376
MPUPSR6
MPU Privilege Select Register region 6
380
MPUPSR7
MPU Privilege Select Register region 7
384
MPUCRA
Unused in this version of AVR32UC
388
MPUCRB
Unused in this version of AVR32UC
392
MPUBRA
Unused in this version of AVR32UC
396
MPUBRB
Unused in this version of AVR32UC
400
MPUAPRA
MPU Access Permission Register A
404
MPUAPRB
MPU Access Permission Register B
408
MPUCR
MPU Control Register
412-764
Reserved
Reserved for future use
768-1020
IMPL
IMPLEMENTATION DEFINED
AT32UC3A
Table 9-4 on page
32. Most of the han-
29