IC MCU AVR32 128KB FLASH 144LQFP

AT32UC3A0128-ALUT

Manufacturer Part NumberAT32UC3A0128-ALUT
DescriptionIC MCU AVR32 128KB FLASH 144LQFP
ManufacturerAtmel
SeriesAVR®32 UC3
AT32UC3A0128-ALUT datasheets
 

Specifications of AT32UC3A0128-ALUT

Core ProcessorAVRCore Size32-Bit
Speed66MHzConnectivityEBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o109
Program Memory Size128KB (128K x 8)Program Memory TypeFLASH
Ram Size32K x 8Voltage - Supply (vcc/vdd)1.65 V ~ 1.95 V
Data ConvertersA/D 8x10bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case144-LQFP
Processor SeriesAT32UC3xCoreAVR32
Data Bus Width32 bitData Ram Size32 KB
Interface Type2-Wire, RS-485, SPI, USARTMaximum Clock Frequency66 MHz
Number Of Programmable I/os69Number Of Timers3
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
3rd Party Development ToolsEWAVR32, EWAVR32-BL, KSK-EVK1100-PLDevelopment Tools By SupplierATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature- 40 CController Family/seriesAT32UC3A
No. Of I/o's109Ram Memory Size32KB
Cpu Speed66MHzNo. Of Timers1
Rohs CompliantYesFor Use WithATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
show all specifications
ATEVK1104 PDF datasheetAT32UC3A0128-ALUT PDF datasheet #2
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41.2
Rev. J
41.2.1
PWM
1. PWM channel interrupt enabling triggers an interrupt
When enabling a PWM channel that is configured with center aligned period (CALG=1), an
interrupt is signalled.
Fix/Workaround
When using center aligned mode, enable the channel and read the status before channel
interrupt is enabled.
2. PWM counter restarts at 0x0001
The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first
PWM period has one more clock cycle.
Fix/Workaround
- The first period is 0x0000, 0x0001, ..., period
- Consecutive periods are 0x0001, 0x0002, ..., period
3. PWM update period to a 0 value does not work
It is impossible to update a period equal to 0 by the using the PWM update register
(PWM_CUPD).
Fix/Workaround
Do not update the PWM_CUPD register with a value equal to 0.
41.2.2
ADC
1. Sleep Mode activation needs additional A to D conversion
If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode
before after the next AD conversion.
Fix/Workaround
Activate the sleep mode in the mode register and then perform an AD conversion.
41.2.3
SPI
1. SPI Slave / PDCA transfer: no TX UNDERRUN flag
There is no TX UNDERRUN flag available, therefore in SPI slave mode, there is no way to
be informed of a character lost in transmission.
Fix/Workaround
For PDCA transfer: none.
2. SPI FDIV option does not work
Selecting clock signal using FDIV = 1 does not work as specified.
Fix/Workaround
Do not set FDIV = 1.
3. SPI Bad Serial Clock Generation on 2nd chip_select when SCBR = 1, CPOL=1 and
NCPHA=0
When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't
equal to 1, and CPOL=1 and CPHA=0, then an aditional pulse will be generated on SCK.
Fix/workaround
32058J–AVR32–04/11
796

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