AT32UC3A0128-ALUT Atmel, AT32UC3A0128-ALUT Datasheet - Page 741

IC MCU AVR32 128KB FLASH 144LQFP

AT32UC3A0128-ALUT

Manufacturer Part Number
AT32UC3A0128-ALUT
Description
IC MCU AVR32 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets

Specifications of AT32UC3A0128-ALUT

Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, RS-485, SPI, USART
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
36. JTAG and Boundary Scan
36.1
36.2
32058J–AVR32–04/11
Features
Overview
Rev.: 2.0.0.2
Figure 36-1 on page 742
troller is a state machine controlled by the TCK and TMS signals. The TAP Controller selects
either the JTAG Instruction Register or one of several Data Registers as the scan chain (shift
register) between the TDI-input and TDO-output. The Instruction Register holds JTAG instruc-
tions controlling the behavior of a Data Register.
The ID Register, Bypass Register, and the Boundary-Scan Chain are the Data Registers used
for board-level testing. The Reset Register can be used to keep the device reset during test or
programming.
The Service Access Bus (SAB) interface contains address and data registers for the Service
Access Bus, which gives access to on-chip debug, programming, and other functions in the
device. The SAB offers several modes of access to the address and data registers, as dis-
cussed in
Section 36.7
document.
IEEE1149.1 compliant JTAG Interface
Boundary-Scan Chain for board-level testing
Direct memory access and programming capabilities through JTAG interface
On-Chip Debug access in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0)
Section
lists the supported JTAG instructions, with references to the description in this
36.6.4.
shows how the JTAG is connected in an AVR32 device. The TAP Con-
AT32UC3A
741

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