AT32UC3A0128-ALUT Atmel, AT32UC3A0128-ALUT Datasheet - Page 445

IC MCU AVR32 128KB FLASH 144LQFP

AT32UC3A0128-ALUT

Manufacturer Part Number
AT32UC3A0128-ALUT
Description
IC MCU AVR32 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets

Specifications of AT32UC3A0128-ALUT

Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, RS-485, SPI, USART
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
32058J–AVR32–04/11
its current contents and regardless of the state of the configuration register bit 13. An interrupt
(12) is triggered when a pause frame is received, assuming it is enabled in the interrupt mask
register. If bit 13 is set in the network configuration register and the value of the pause time reg-
ister is non-zero, no new frame is transmitted until the pause time register has decremented to
zero.
The loading of a new pause time, and hence the pausing of transmission, only occurs when the
MACB is configured for full-duplex operation. If the MACB is configured for half-duplex, there is
no transmission pause, but the pause frame received interrupt is still triggered.
A valid pause frame is defined as having a destination address that matches either the address
stored in specific address register 1 or matches 0x0180C2000001 and has the MAC control
frame type ID of 0x8808 and the pause opcode of 0x0001. Pause frames that have FCS or other
errors are treated as invalid and are discarded. Valid pause frames received increment the
Pause Frame Received statistic register.
The pause time register decrements every 512 bit times (i.e., 128 rx_clks in nibble mode)
once transmission has stopped. For test purposes, the register decrements every rx_clk cycle
once transmission has stopped if bit 12 (retry test) is set in the network configuration register. If
the pause enable bit (13) is not set in the network configuration register, then the decrementing
occurs regardless of whether transmission has stopped or not.
An interrupt (13) is asserted whenever the pause time register decrements to zero (assuming it
is enabled in the interrupt mask register). Automatic transmission of pause frames is supported
through the transmit pause frame bits of the network control register and the tx_pause and
tx_pause_zero inputs. If either bit 11 or bit 12 of the network control register is written to with
a 1, or if the input signal tx_pause is toggled, a pause frame is transmitted only if full duplex is
selected in the network configuration register and transmit is enabled in the network control
register.
Pause frame transmission occurs immediately if transmit is inactive or if transmit is active
between the current frame and the next frame due to be transmitted. The transmitted pause
frame is comprised of the items in the following list:
The pause quantum used in the generated frame depends on the trigger source for the frame as
follows:
• a destination address of 01-80-C2-00-00-01
• a source address taken from the specific address 1 register
• a type ID of 88-08 (MAC control frame)
• a pause opcode of 00-01
• a pause quantum
• fill of 00 to take the frame to minimum frame length
• valid FCS
1. If bit 11 is written with a one, the pause quantum comes from the transmit pause quan-
2. If bit 12 is written with a one, the pause quantum is zero.
3. If the tx_pause input is toggled and the tx_pause_zero input is held low until the
4. If the tx_pause input is toggled and the tx_pause_zero input is held high until the
tum register. The Transmit Pause Quantum register resets to a value of 0xFFFF giving
a maximum pause quantum as a default.
next toggle, the pause quantum comes from the transmit pause quantum register.
next toggle, the pause quantum is zero.
AT32UC3A
445

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