AT32UC3A0128-ALUT Atmel, AT32UC3A0128-ALUT Datasheet - Page 58

IC MCU AVR32 128KB FLASH 144LQFP

AT32UC3A0128-ALUT

Manufacturer Part Number
AT32UC3A0128-ALUT
Description
IC MCU AVR32 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets

Specifications of AT32UC3A0128-ALUT

Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, RS-485, SPI, USART
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
13.5.5
13.5.5.1
13.5.5.2
32058J–AVR32–04/11
PLL0 clock
Osc0 clock
Slow clock
Synchronous clocks
Selecting synchronous clock division ratio
Selecting PLL or oscillator for the main clock
MCSEL
The slow clock (default), Oscillator 0, or PLL0 provide the source for the main clock, which is the
common root for the synchronous clocks for the CPU/HSB, PBA, and PBB modules. The main
clock is divided by an 8-bit prescaler, and each of these four synchronous clocks can run from
any tapping of this prescaler, or the undivided main clock, as long as f
nous clock source can be changed on-the fly, responding to varying load in the application. The
clock domains can be shut down in sleep mode, as described in
Additionally, the clocks for each module in the four domains can be individually masked, to avoid
power consumption in inactive modules.
Figure 13-4. Synchronous clock generation
The common main clock can be connected to the slow clock, Oscillator 0, or PLL0. By default,
the main clock will be connected to the slow clock. The user can connect the main clock to Oscil-
lator 0 or PLL0 by writing the MCSEL bitfield in the Main Clock Control Register (MCCTRL). This
must only be done after that unit has been enabled, otherwise a deadlock will occur. Care
should also be taken that the new frequency of the synchronous clocks does not exceed the
maximum frequency for each clock domain.
The main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks.
By default, the synchronous clocks run on the undivided main clock. The user can select a pres-
Prescaler
instruction
Sleep
CPUSEL
CPUDIV
0
1
Controller
Main clock
Sleep
CPUMASK
Mask
”Sleep modes” on page
CPU
AT32UC3A
f
PBA,B,
CPU clocks
HSB clocks
PBB clocks
PBAclocks
. The synchro-
60.
58

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