LPC2102FBD48,151 NXP Semiconductors, LPC2102FBD48,151 Datasheet - Page 14

• Manufacturer Part Number: LPC2102FBD48,151
• Description: IC ARM7 MCU FLASH 16K 48-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2100r

Specifications of LPC2102FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 70MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC21
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 4 KB
• Interface Type: I2C/JTAG/SPI/SSP/UART
• Maximum Clock Frequency: 70 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: LPC2000
• Device Core: ARM7TDMI-S
• Device Core Size: 16/32Bit
• Frequency (max): 70MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC2000
• Maximum Speed: 70 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4310 - EVAL BOARD LPC2158 W/LCD568-4297 - BOARD EVAL LPC21XX MCB2100MCB2103UME - BOARD EVAL MCB2103 + ULINK-MEMCB2103U - BOARD EVAL MCB2103 + ULINK2MCB2103 - BOARD EVAL NXP LPC2101/2101/2103622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-2093; 935280965151; LPC2102FBD48-S

NXP Semiconductors
LPC2101_02_03_4
Product data sheet
6.10.1 Features
6.11.1 Features
6.10 I
6.11 SPI serial I/O controller
The LPC2101/02/03 each contain two I
The I
(SCL), and a Serial Data Line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., LCD driver) or a transmitter with the
capability to both receive and send information such as serial memory. Transmitters
and/or receivers can operate in either master or slave mode, depending on whether the
chip has to initiate a data transfer or is only addressed. The I
it can be controlled by more than one bus master connected to it.
The I
I
The LPC2101/02/03 each contain one SPI controller. The SPI is a full duplex serial
interface, designed to handle multiple masters and slaves connected to a given bus. Only
a single master and a single slave can communicate on the interface during a given data
transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the
slave, and the slave always sends 8 bits to 16 bits of data to the master.
2
2
•
•
•
C-bus).
•
•
•
•
•
•
•
•
•
•
•
C-bus serial I/O controllers
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
Transmission FIFO control enables implementation of software (XON/XOFF) flow
control on both UARTs.
UART1 is equipped with standard modem interface signals. This module also
provides full support for hardware flow control (auto-CTS/RTS).
Compliant with standard I
Easy to configure as Master, Slave, or Master/Slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
Compliant with SPI specification.
Synchronous, Serial, Full Duplex, Communication.
2
2
C-bus is bidirectional, for inter-IC control using only two wires: a Serial Clock Line
C-bus implemented in LPC2101/02/03 supports bit rates up to 400 kbit/s (Fast
2
C-bus can also be used for test and diagnostic purposes.
Rev. 04 — 2 June 2009
2
C-bus interface.
2
C-bus controllers.
Single-chip 16-bit/32-bit microcontrollers
LPC2101/02/03
2
C-bus is a multi-master bus,
© NXP B.V. 2009. All rights reserved.
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