LPC2102FBD48,151 NXP Semiconductors, LPC2102FBD48,151 Datasheet - Page 19

• Manufacturer Part Number: LPC2102FBD48,151
• Description: IC ARM7 MCU FLASH 16K 48-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2100r

Specifications of LPC2102FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 70MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC21
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 4 KB
• Interface Type: I2C/JTAG/SPI/SSP/UART
• Maximum Clock Frequency: 70 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: LPC2000
• Device Core: ARM7TDMI-S
• Device Core Size: 16/32Bit
• Frequency (max): 70MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC2000
• Maximum Speed: 70 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4310 - EVAL BOARD LPC2158 W/LCD568-4297 - BOARD EVAL LPC21XX MCB2100MCB2103UME - BOARD EVAL MCB2103 + ULINK-MEMCB2103U - BOARD EVAL MCB2103 + ULINK2MCB2103 - BOARD EVAL NXP LPC2101/2101/2103622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-2093; 935280965151; LPC2102FBD48-S

NXP Semiconductors
LPC2101_02_03_4
Product data sheet
CAUTION
6.17.4 Code security (Code Read Protection - CRP)
6.17.5 External interrupt inputs
6.17.6 Memory mapping control
6.17.7 Power control
This feature of the LPC2101/02/03 allows user to enable different levels of security in the
system so that access to the on-chip flash and use of the JTAG and ISP can be restricted.
When needed, CRP is invoked by programming a specific pattern into a dedicated flash
location. IAP commands are not affected by the CRP.
Implemented in bootloader code version 2.21 are three levels of the Code Read
Protection:
Remark: Parts LPC2101/02/03 Revision ‘-’ have CRP2 enabled only (bootloader code
version 2.2).
The LPC2101/02/03 include up to three edge or level sensitive external interrupt inputs as
selectable pin functions. When the pins are combined, external events can be processed
as three independent interrupt signals. The external interrupt inputs can optionally be
used to wake-up the processor from Power-down mode and Deep power-down mode.
Additionally all 10 capture input pins can also be used as external interrupts without the
option to wake the device up from Power-down mode.
The memory mapping control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip
flash memory, or to the on-chip static RAM. This allows code running in different memory
spaces to have control of the interrupts.
The LPC2101/02/03 supports three reduced power modes: Idle mode, Power-down
mode, and Deep power-down mode.
1. CRP1 disables access to chip via the JTAG and allows partial flash update (excluding
2. CRP2 disables access to chip via the JTAG and only allows full flash erase and
3. Running an application with level CRP3 selected fully disables any access to chip via
flash sector 0) using a limited set of the ISP commands. This mode is useful when
CRP is required and flash field updates are needed but all sectors cannot be erased.
update using a reduced set of the ISP commands.
the JTAG pins and the ISP. This mode effectively disables ISP override using P0.14
pin, too. It is up to the user’s application to provide (if needed) flash update
mechanism using IAP calls or call reinvoke ISP command to enable flash update via
UART0.
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
Rev. 04 — 2 June 2009
Single-chip 16-bit/32-bit microcontrollers
LPC2101/02/03
© NXP B.V. 2009. All rights reserved.
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