P87C654X2BBD,157 NXP Semiconductors, P87C654X2BBD,157 Datasheet - Page 31

• Manufacturer Part Number: P87C654X2BBD,157
• Description: IC 80C51 MCU 16K OTP 44-LQFP
• Manufacturer: NXP Semiconductors
• Series: 87Cr

Specifications of P87C654X2BBD,157

• Program Memory Type: OTP
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 44-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: I²C, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 32
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Processor Series: P87C6x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, UART
• Maximum Clock Frequency: 16 MHz, 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-3202; 935272902157; P87C654X2BBD

Philips Semiconductors
I
on-chip I
describes the individual blocks.
I
The input filters have I
voltage is less than 1.5 V, the input logic level is interpreted as 0; if
the input voltage is greater than 3.0 V, the input logic level is
interpreted as 1. Input signals are synchronized with the internal
clock (f
filtered out.
The output stages consist of open drain transistors that can sink
3mA at V
clamping diodes to V
I
A
This 8-bit special function register may be loaded with the 7-bit slave
address (7 most significant bits) to which the I
2004 Apr 20
2
NPUT
2
DDRESS
C-bus Implementation and Operation: Figure 23 shows how the
C-bus and V
SDA
SCL
80C51 8-bit microcontroller family
256B RAM, low voltage (2.7 to 5.5 V), low power, high speed
(30/33 MHz)
CONDITION
F
OSC
ILTERS AND
START
2
OUT
R
C-bus interface is implemented, and the following text
S
EGISTER,
/4), and spikes shorter than three oscillator periods are
< 0.4 V. These open drain outputs do not have
DD
I
2
C-bus
is switched off, the I
MSB
O
S
UTPUT
1
DD
1
2
ADR
C-bus compatible input levels. If the input
. Thus, if the device is connected to the
SLAVE ADDRESS
S
TAGES
2
P1.7/SDA
P8xC654X2
2
C-bus is not affected.
P1.6/SCL
7
16 kB OTP/ROM,
2
C-bus will respond
DIRECTION
Figure 21. Typical I
Figure 22. Data Transfer on the I
SIGNAL FROM RECEIVER
ACKNOWLEDGMENT
R/W
BIT
8
OTHER DEVICE WITH
ACK
I
2
9
C-BUS INTERFACE
R
P
31
2
C-bus configuration
R
when programmed as a slave transmitter or receiver. The LSB (GC)
is used to enable general call address (00H) recognition.
C
The comparator compares the received 7-bit slave address with its
own slave address (7 most significant bits in S1ADR). It also
compares the first received 8-bit byte with the general call address
(00H). If an equality is found, the appropriate status bits are set and
an interrupt is requested.
S
This 8-bit special function register contains a byte of serial data to
be transmitted or a byte which has just been received. Data in
S1DAT is always shifted from right to left; the first bit to be
transmitted is the MSB (bit 7) and, after a byte has been received,
the first bit of received data is located at the MSB of S1DAT. While
data is being shifted out, data on the bus is simultaneously being
shifted in; S1DAT always contains the last byte present on the bus.
Thus, in the event of lost arbitration, the transition from master
transmitter to slave receiver is made with the correct data in S1DAT.
P
HIFT
OMPARATOR
V
1
CLOCK LINE HELD LOW WHILE
INTERRUPTS ARE SERVICED
DD
R
EGISTER,
REPEATED IF MORE BYTES
ARE TRANSFERRED
2
C-bus
2
S
OTHER DEVICE WITH
1
I
2
DAT
C-BUS INTERFACE
SIGNAL FROM RECEIVER
3–8
ACKNOWLEDGMENT
P83C654X2/P87C654X2
ACK
9
SU01734
SDA
SCL
P/S
Product data
CONDITION
CONDITION
REPEATED
SU00965
START
STOP