P87C654X2BBD,157 NXP Semiconductors, P87C654X2BBD,157 Datasheet - Page 36

• Manufacturer Part Number: P87C654X2BBD,157
• Description: IC 80C51 MCU 16K OTP 44-LQFP
• Manufacturer: NXP Semiconductors
• Series: 87Cr

Specifications of P87C654X2BBD,157

• Program Memory Type: OTP
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 44-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: I²C, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 32
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Processor Series: P87C6x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, UART
• Maximum Clock Frequency: 16 MHz, 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-3202; 935272902157; P87C654X2BBD

SI = 0: When the SI flag is reset, no serial interrupt is requested, and
Philips Semiconductors
If the STA and STO bits are both set, the a STOP condition is
transmitted to the I
mode, I
transmitted). I
STO = 0: When the STO bit is reset, no STOP condition will be
generated.
SI
SI = 1: When the SI flag is set, then, if the EA and ES1 (interrupt
enable register) bits are also set, a serial interrupt is requested. SI is
set by hardware when one of 25 of the 26 possible I
entered. The only state that does not cause SI to be set is state
F8H, which indicates that no relevant state information is available.
While SI is set, the LOW period of the serial clock on the SCL line is
stretched, and the serial transfer is suspended. A HIGH level on the
SCL line is unaffected by the serial interrupt flag. SI must be reset
by software.
there is no stretching of the serial clock on the SCL line.
AA
AA = 1: If the AA flag is set, an acknowledge (low level to SDA) will
be returned during the acknowledge clock pulse on the SCL line
when:
– The “own slave address” has been received
– The general call address has been received while the general call
– A data byte has been received while I
– A data byte has been received while I
AA = 0: if the AA flag is reset, a not acknowledge (HIGH level to
SDA) will be returned during the acknowledge clock pulse on SCL
when:
– A data has been received while I
– A data byte has been received while I
When I
be entered after the last serial is transmitted (see Figure 31). When
SI is cleared, I
receiver mode, and the SDA line remains at a HIGH level. In state
C8H, the AA flag can be set again for future address recognition.
2004 Apr 20
, THE
bit (GC) in S1ADR is set
mode
receiver mode
receiver mode
80C51 8-bit microcontroller family
256B RAM, low voltage (2.7 to 5.5 V), low power, high speed
(30/33 MHz)
, THE
2
S
2
A
C is in the addressed slave transmitter mode, state C8H will
C generates an internal STOP condition which is not
ERIAL
SSERT
2
2
I
C then transmits a START condition.
NTERRUPT
C leaves state C8H, enters the not addressed slave
A
CKNOWLEDGE
2
C-bus if I
F
LAG
2
C is in a master mode (in a slave
F
LAG
2
C is in the master receiver mode
2
2
2
C is in the master receiver
C is in the addressed slave
C is in the addressed slave
16 kB OTP/ROM,
2
C states is
36
When I
and the general call address are ignored. Consequently, no
acknowledge is returned, and a serial interrupt is not requested.
Thus, I
bus status is monitored. While I
and STOP conditions are detected, and serial data is shifted in.
Address recognition can be resumed at any time by setting the AA
flag. If the AA flag is set when the part’s own slave address or the
general call address has been partly received, the address will be
recognized at the end of the byte transmission.
CR
These three bits determine the serial clock frequency when I
a master mode. The various serial rates are shown in Table 7.
If the I
set. The user can read but cannot write (write once) to AUXR after
setup.
A 12.5kHz bit rate may be used by devices that interface to the
I
slow. 100kHz is usually the maximum bit rate and can be derived
from a 16 MHz, 12 MHz, or a 6 MHz oscillator. A variable bit rate
(0.5kHz to 62.5kHz) may also be used if Timer 1 is not required for
any other purpose while I
The frequencies shown in Table 7 are unimportant when I
slave mode. In the slave modes, I
with any clock frequency up to 100kHz.
The Status Register, S1STA: S1STA is an 8-bit read-only special
function register. The three least significant bits are always zero.
The five most significant bits contain the status code. There are 26
possible status codes. When S1STA contains F8H, no relevant state
information is available and no serial interrupt is requested. All other
S1STA values correspond to defined I
these states is entered, a serial interrupt is requested (SI = 1). A
valid status code is present in S1STA one machine cycle after SI is
set by hardware and is still present one machine cycle after SI has
been reset by software.
2
AUXR
(8EH)
C-bus via standard I/O port lines which are software driven and
0,
CR
2
2
2
C block is to be used in fast mode, bit 3 in AUXR must be
C can be temporarily released from the I
C is in the not addressed slave mode, its own slave address
1, AND
CR
7
–
2, THE
6
–
P83C654X2/P87C654X2
C
2
LOCK
C is in a master mode.
5
–
2
R
C is released from the bus, START
ATE
2
C will automatically synchronize
4
–
B
2
ITS
C states. When each of
FAST/
STD
I
2
3
C
2
C-bus while the
2
–
Product data
1
–
2
C is in a
2
C is in
A0
0