P87C654X2BBD,157 NXP Semiconductors, P87C654X2BBD,157 Datasheet - Page 61

• Manufacturer Part Number: P87C654X2BBD,157
• Description: IC 80C51 MCU 16K OTP 44-LQFP
• Manufacturer: NXP Semiconductors
• Series: 87Cr

Specifications of P87C654X2BBD,157

• Program Memory Type: OTP
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 44-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: I²C, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 32
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Processor Series: P87C6x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, UART
• Maximum Clock Frequency: 16 MHz, 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-3202; 935272902157; P87C654X2BBD

1. L = Level activated
2. T = Transition activated
Philips Semiconductors
Interrupt Priority Structure
The P8xC654X2 has an 8 source four-level interrupt structure (see
Table 14).
There are four SFRs associated with the four-level interrupt. They
are IE, IEN1, IP, and IPH. The IPH (Interrupt Priority High) register
makes the four-level interrupt structure possible. The IPH is located
at SFR address B7H. The structure of the IPH register and a
description of its bits is shown in Figure 38.
Table 14.
NOTES:
The priority scheme for servicing the interrupts is the same as that
for the 80C51, except there are four interrupt levels rather than two
as on the 80C51. An interrupt will be serviced as long as an interrupt
of equal or higher priority is not already being serviced. If an
interrupt of equal or higher level priority is being serviced, the new
2004 Apr 20
80C51 8-bit microcontroller family
256B RAM, low voltage (2.7 to 5.5 V), low power, high speed
(30/33 MHz)
SI01 (I2C)
SOURCE
BIT
IE.7
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
SP
X0
T0
X1
T1
T2
Interrupt Table
IE (0A8H)
SYMBOL
EA
–
ET2
ES
ET1
EX1
ET0
EX0
POLLING PRIORITY
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
FUNCTION
Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.
–
Timer 2 interrupt enable bit.
Serial Port interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enable bit.
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
EA
7
1
2
3
4
5
6
7
16 kB OTP/ROM,
6
–
ET2
5
Figure 36. IE Registers
REQUEST BITS
ES
4
TF2, EXF2
RI, TI
TP0
TF1
IE0
IE1
61
–
ET1
3
The function of the IPH SFR, when combined with the IP SFR,
determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
interrupt will wait until it is finished before being serviced. If a lower
priority level interrupt is being serviced, it will be stopped and the
new interrupt serviced. When the new interrupt is finished, the lower
priority level interrupt that was stopped will be completed.
IPH.x
PRIORITY BITS
0
0
1
1
EX1
2
HARDWARE CLEAR?
N (L)
ET0
N (L) Y (T)
IP.x
1
0
1
0
1
P83C654X2/P87C654X2
1
N
Y
Y
N
N
Y (T)
EX0
0
Level 0 (lowest priority)
Level 1
Level 2
Level 3 (highest priority)
2
INTERRUPT PRIORITY LEVEL
INTERRUPT PRIORITY LEVEL
VECTOR ADDRESS
SU01745
2BH
0BH
1BH
3BH
03H
13H
23H
Product data