P87C654X2BBD,157 NXP Semiconductors, P87C654X2BBD,157 Datasheet - Page 49

• Manufacturer Part Number: P87C654X2BBD,157
• Description: IC 80C51 MCU 16K OTP 44-LQFP
• Manufacturer: NXP Semiconductors
• Series: 87Cr

Specifications of P87C654X2BBD,157

• Program Memory Type: OTP
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 44-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: I²C, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 32
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Processor Series: P87C6x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, UART
• Maximum Clock Frequency: 16 MHz, 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-3202; 935272902157; P87C654X2BBD

Philips Semiconductors
Software Examples of I
consists of a software example for:
– Initialization of I
– Entering the I
– The 26 state service routines for the
I
In the initialization routine, I
modes. For each mode, a number of bytes of internal data RAM are
allocated to the SIO to act as either a transmission or reception
buffer. In this example, 8 bytes of internal data RAM are reserved for
different purposes. The data memory map is shown in Figure 35.
The initialization routine performs the following functions:
– S1ADR is loaded with the part’s own slave address and the
– P1.6 and P1.7 bit latches are loaded with logic 1s
– RAM location HADD is loaded with the high-order address byte of
– The I
– The slave mode is enabled by simultaneously setting the ENS1
The I
address and general call. If the general call or the own slave
address is detected, an interrupt is requested and S1STA is loaded
with the appropriate state information. The following text describes a
fast method of branching to the appropriate service routine.
2004 Apr 20
NITIALIZATION
general call bit (GC)
the service routines
and AA bits in S1CON and the serial clock frequency (for master
modes) is defined by loading CR0 and CR1 in S1CON. The
master routines must be started in the main program.
80C51 8-bit microcontroller family
256B RAM, low voltage (2.7 to 5.5 V), low power, high speed
(30/33 MHz)
– Master transmitter mode
– Master receiver mode
– Slave receiver mode
– Slave transmitter mode
2
C hardware now begins checking the I
2
(1) Unsuccessful attempt to send a Start condition
(2) SDA line released
(3) Successful attempt to send a Start condition; state 08H is entered
C interrupt enable and interrupt priority bits are set
STA FLAG
SDA LINE
SCL LINE
2
C interrupt routine
2
C after a RESET
2
C Service Routines: This section
2
C is enabled for both master and slave
Figure 34. Recovering from a Bus Obstruction Caused by a Low Level on SDA
(1)
2
C-bus for its own slave
16 kB OTP/ROM,
(1)
49
The state service routines are located in a 256-byte page of program
I
When the I
stack. Then S1STA and HADD (loaded with the high-order address
byte of the 26 service routines by the initialization routine) are
pushed on to the stack. S1STA contains a status code which is the
lower byte of one of the 26 service routines. The next instruction is
RET, which is the return from subroutine instruction. When this
instruction is executed, the HIGH and LOW order address bytes are
popped from stack and loaded into the program counter.
The next instruction to be executed is the first instruction of the state
service routine. Seven bytes of program code (which execute in
eight machine cycles) are required to branch to one of the 26 state
service routines.
SI
memory. The location of this page is defined in the initialization
routine. The page can be located anywhere in program memory by
loading data RAM register HADD with the page number. Page 01 is
chosen in this example, and the service routines are located
between addresses 0100H and 01FFH.
T
The state service routines are located 8 bytes from each other. Eight
bytes of code are sufficient for most of the service routines. A few of
the routines require more than 8 bytes and have to jump to other
locations to obtain more bytes of code. Each state routine is part of
the I
with a RETI instruction which causes a return to the main program.
2
HE
C I
NTERRUPT
S
2
C interrupt routine and handles one of the 26 states. It ends
TATE
PUSH PSW
PUSH S1STA
PUSH HADD
RET
S
2
C interrupt is entered, the PSW is first pushed on the
(2)
ERVICE
START CONDITION
R
OUTINE
R
OUTINES
P83C654X2/P87C654X2
(3)
Save PSW
Push status code
(low order address byte)
Push HIGH order address byte
Jump to state service routine
SU00977
Product data