LPC2138FHN64/01,55 NXP Semiconductors, LPC2138FHN64/01,55 Datasheet - Page 18

• Manufacturer Part Number: LPC2138FHN64/01,55
• Description: IC ARM7 MCU FLASH 512K 64-HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC2100r

Specifications of LPC2138FHN64/01,55

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 47
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC21
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C/SPI/SSP/UART
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 2
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC2138, KSK-LPC2138-PL
• Development Tools By Supplier: OM10045, OM10070, OM10089
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4310 - EVAL BOARD LPC2158 W/LCD568-4298 - BOARD EVAL LPC213X KS213X568-4297 - BOARD EVAL LPC21XX MCB2100MCB2130UME - BOARD EVAL MCB2130 + ULINK-MEMCB2130U - BOARD EVAL MCB2130 + ULINK2MCB2130 - BOARD EVAL NXP LPC213X ARM FAM622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K568-2095 - BOARD EVAL FOR LPC213X ARM MCU
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4011; 935281779557; LPC2138FHN64/01

NXP Semiconductors
LPC2131_32_34_36_38
Product data sheet
6.10.2 UART features available in LPC213x/01 only
6.11.1 Features
6.12 SPI serial I/O controller
6.11 I
The LPC2131/32/34/36/38 each contain two I
The I
(SCL), and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the
capability to both receive and send information (such as memory)). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
controlled by more than one bus master connected to it.
This I
The LPC2131/32/34/36/38 each contain one SPI controller. The SPI is a full duplex serial
interface, designed to be able to handle multiple masters and slaves connected to a given
bus. Only a single master and a single slave can communicate on the interface during a
given data transfer. During a data transfer the master always sends a byte of data to the
slave, and the slave always sends a byte of data to the master.
2
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•
•
•
•
•
•
•
•
•
•
•
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C-bus serial I/O controller
Built-in baud rate generator.
Standard modem interface signals included on UART1. (LPC2134/36/38 only)
The LPC2131/32/34/36/38 transmission FIFO control enables implementation of
software (XON/XOFF) flow control on both UARTs and hardware (CTS/RTS) flow
control on the LPC2134/36/38 UART1 only.
Fractional baud rate generator enables standard baud rates such as 115200 to be
achieved with any crystal frequency above 2 MHz.
Auto-bauding.
Auto-CTS/RTS flow-control fully implemented in hardware (LPC2134/36/38 only).
Standard I
Easy to configure as Master, Slave, or Master/Slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
2
2
C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line
C-bus implementation supports bit rates up to 400 kbit/s (Fast I
2
C-bus may be used for test and diagnostic purposes.
2
C compliant bus interface.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 2 February 2011
LPC2131/32/34/36/38
2
C-bus controllers.
Single-chip 16/32-bit microcontrollers
2
C-bus is a multi-master bus, it can be
2
C).
© NXP B.V. 2011. All rights reserved.
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