ST7FLIT19BF1B6 STMicroelectronics, ST7FLIT19BF1B6 Datasheet - Page 70

• Manufacturer Part Number: ST7FLIT19BF1B6
• Description: IC MCU 8BIT 4K FLASH 20DIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLIT19BF1B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: ST7FLIT1x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLIT1B-D/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit , 13 bit, 7 Channel
• For Use With: 497-6232 - BOARD EVAL ST7LITE1B,STP5NK60Z497-5049 - KIT STARTER RAISONANCE ST7FLITE497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5626-5

ST7LITE1xB
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
11.2.3.7 Force Update
In order not to wait for the counter
load the value into active DCRx registers, a pro-
grammable counter
both counters, a separate bit is provided which
when set, make the counters start with the over-
flow value, i.e. FFFh. After overflow, the counters
start counting from their respective auto reload
register values.
These bits are FORCE1 and FORCE2 in the
ATCSR2 register. FORCE1 is used to force an
overflow on Counter 1 and, FORCE2 is used for
Counter 2. These bits are set by software and re-
Figure 50. Force Overflow Timing Diagram
70/159
1
FORCE2 FORCE1
FORCEx
CNTRx
f
CNTRx
x
ATCSR2 Register
overflow is provided. For
E03
E04
x
overflow to
FFF
ATRx
set by hardware after the respective counter over-
flow event has occurred.
This feature can be used at any time. All related
features such as PWM generation, Output Com-
pare, Input Capture, One-pulse (refer to
Dynamic DCR2/3 update in One Pulse
be used this way.
Mode) can
Figure 15.