ST7FLIT19BF1B6 STMicroelectronics, ST7FLIT19BF1B6 Datasheet - Page 86

• Manufacturer Part Number: ST7FLIT19BF1B6
• Description: IC MCU 8BIT 4K FLASH 20DIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLIT19BF1B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: ST7FLIT1x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLIT1B-D/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit , 13 bit, 7 Channel
• For Use With: 497-6232 - BOARD EVAL ST7LITE1B,STP5NK60Z497-5049 - KIT STARTER RAISONANCE ST7FLITE497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5626-5

ST7LITE1xB
SERIAL PERIPHERAL INTERFACE (cont’d)
11.4.3.1 Functional Description
A basic example of interconnections between a
single master and a single slave is illustrated in
Figure
The MOSI pins are connected together and the
MISO pins are connected together. In this way
data is transferred serially between master and
slave (most significant bit first).
The communication is always initiated by the mas-
ter. When the master device transmits data to a
slave device via MOSI pin, the slave device re-
sponds by sending data to the master device via
Figure 54. Single Master/ Single Slave Application
86/159
1
2.
MSBit
GENERATOR
8-bit SHIFT REGISTER
CLOCK
SPI
MASTER
LSBit
MOSI
SCK
SS
MISO
+5V
the MISO pin. This implies full duplex communica-
tion with both data out and data in synchronized
with the same clock signal (which is provided by
the master device via the SCK pin).
To use a single data line, the MISO and MOSI pins
must be connected at each node (in this case only
simplex communication is possible).
Four possible data/clock timing relationships may
be chosen (see
and slave must be programmed with the same tim-
ing mode.
MISO
MOSI
SCK
SS
Figure 5 on page
MSBit
Not used if SS is managed
by software
8-bit SHIFT REGISTER
SLAVE
7) but master
LSBit