Z16F3211FI20SG Zilog, Z16F3211FI20SG Datasheet - Page 206

• Manufacturer Part Number: Z16F3211FI20SG
• Description: IC ZNEO MCU FLASH 32K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F3211FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F3x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 2 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4569

PS022008-0810
DMA Interface
ESPI error interrupts occur if any of the
register are set. These bits are cleared by writing a 1 to the corresponding bit.
If the ESPI is disabled (
timeout. This timer function must be enabled by setting the
register. This timer interrupt does not set any of the bits of the ESPI Status register.
The assertion of the TDRE and RDRF signals generate transmit and receive DMA
requests (SPITxReq, SPIRxReq), allowing data movement to be handled by a DMA
controller rather than directly by software. The DMA acknowledges these requests
through the SPITxAck and SPIRxAck signals). Inputs allow the
Transmit Data Command register to be controlled by the DMA. The SPITxReqEOF and
SPIRxReqEOF outputs to the DMA provides an indication that SS has deasserted
(transaction complete).
If the software application is moving data in only one direction, the
set to 10 or 01, allowing a single DMA channel to control the ESPI data transfer. For a
master, the valid options are transmit only or transmit-receive. For a slave, all options are
valid. When a slave is operating in receive only mode, it will transmit characters of all 1s.
DMA Descriptors
For ESPI Transmit DMA descriptors, the 4-bit
Table 95
controls the ESPI SS output. The SSV bit in the descriptor is transferred to the SSV bit in
the ESPI Data Command register with the first byte of the buffer. If the EOF bit is set in
the DMA descriptor control word, the end of frame signal from the DMA (EOFSync) will
assert coincident with writing the last byte in the buffer to the ESPI Data register, setting
the TEOF bit of the ESPI Data Command register. Once this last byte has been transferred,
the Master’s SS output will deassert and the SSV and TEOF bits in the Data Command
register will be cleared. The
function.
For ESPI DMA descriptors, the 4-bit frame status field of the descriptor has the following
format.
format. The SSV bit in the Master’s transmit buffer descriptor
Table 95. ESPI Tx DMA Descriptor Command Field
Table 96. ESPI Tx DMA Descriptor Status field
Reserved
0
ESPIEN1,0 = 00
Reserved
P R E L I M I N A R Y
CMDSTAT
0
field in ESPI Receive DMA Descriptors has no
Reserved
TUND
COL
), an ESPI interrupt is generated by a BRG 
,
COL
CMDSTAT
,
ABT
Enhanced Serial Peripheral Interface
TUND
SSV
, and
field of the descriptor is in
BRGCTL
ROVR
Product Specification
SSV
ZNEO
bits in the ESPI Status
ESPIEN1,0
bit in the
and
CMDSTAT
TEOF
Z16F Series
ESPICTL
bits of the
bits are
field
190