Z16F3211FI20SG Zilog, Z16F3211FI20SG Datasheet - Page 336

• Manufacturer Part Number: Z16F3211FI20SG
• Description: IC ZNEO MCU FLASH 32K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F3211FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F3x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 2 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4569

PS022008-0810
Table 172. Control Register (DBGCTL)
BIT
FIELD
RESET
R/W
ADDR
Control Register
OCDLOCK
R/W
TXCOL—Transmit Collision
This bit is set when a Transmit Collision occurs. This bit is cleared by writing a one to this
bit.
0 = No collision has been detected.
1 = Transmit Collision has been detected.
RXBUSY—Receiver Busy
This bit is set when the receiver is receiving the data. Multi-master systems uses this bit to
ensure the line is idle before sending the data. 
0 = Receiver is idle.
1 = Receiver is receiving data.
TXBUSY—Transmitter Busy
This bit is set when the transmitter is sending the data. This bit is used to determine when
to turn off a transceiver for RS-485 applications.
0 = Transmitter is idle.
1 = Transmitter is sending the data.
The
OCDLOCK—On-Chip Debug Lock
This bit locks the Debug Control register so it cannot be written by the CPU. This bit is
automatically set if the
0 = Debug Control register unlocked.
1 = Debug Control register locked.
OCDEN—On-chip debug enable
This bit is set when the OCD is enabled. When this bit is set, received data is interpreted as
debug command. To use the DBG pin as a UART or GPIO pin, this bit must be cleared to
zero by software. This bit cannot be written by the CPU if
0 = OCD is disabled.
1 = OCD is enabled.
7
1
Control Register (DBGCTL)
OCDEN
R/W
6
1
DBGUART
5
Reserved
P R E L I M I N A R Y
00
R
option bit is in its default erased state (one). 
sets the mode of the serial interface.
4
FF_E086
CRCEN
R/W
3
1
UARTEN
R/W
OCDLOCK
2
0
Product Specification
ZNEO
ABCHAR ABSRCH
is set.
R/W
On-Chip Debugger
1
0
Z16F Series
R/W
0
1
320