Z16F3211FI20SG Zilog, Z16F3211FI20SG Datasheet - Page 330

• Manufacturer Part Number: Z16F3211FI20SG
• Description: IC ZNEO MCU FLASH 32K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F3211FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F3x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 2 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4569

PS022008-0810
Table 166. On-Chip Debugger Commands (Continued)
Debug Command
Read Memory (short -address is sign
extended)
Write Memory (short -address is sign
extended)
Read Memory (long)
Write Memory (long)
Read Memory CRC
Read Each Memory CRC
Note: Unlisted command byte values are reserved.
Cyclic Redundancy Check
Memory Cyclic Redundancy Check
UART Mode
To ensure transmitted and received data is free of errors, the OCD transmits an 8-bit cyclic
redundancy check (CRC) at the end of each command. The CRC is enabled after the OCD
is initialized, it is not sent with the first read revision command. This CRC is
disabled by clearing the CRCEN bit of the DBGCTL register.
The CRC is reset at the beginning of each command and is computed on the data received
from and sent to the host. The CRC is calculated using the ATM-8 HEC polynomial
x
first. The resulting CRC is reversed and inverted. The check value is
The read memory CRC command computes the CRC on memory in 4K blocks, up to 4K
blocks at a time (16M of data). The Memory CRC is computed using the 16-bit CCITT
polynomial
polynomial LSB first. The resulting CRC is reversed and inverted. The check value is
F0B8h
When the OCD is disabled, the DBG pin is used as a single pin half-duplex UART. When
the serial interface is in UART mode, data received on the single wire bus is written to the
Receive Data register. Data written to the Transmit Data register is transmitted on the sin-
gle wire bus. In UART mode, the auto-baud hardware is used to configure the BRG, or the
baud rate registers are written to set a specific baud rate.
8
+x
2
+x
.
1
+x
x
0
16
. The CRC is preset to all ones. Data is shifted through the polynomial LSB
+x
12
+x
5
+x
P R E L I M I N A R Y
0
. The CRC is preset to all ones. Data is shifted through the
1110-BlockCount[3:0]
1111-BlockCount[3:0]
0100-(regno[3:0])
0100-(regno[3:0])
Command Byte
1010-size[3:0]
1011-size[3:0]
Read only unprotected memory
Read only unprotected memory
Write only unprotected memory
Write only unprotected memory
Disabled by Read Protect
Product Specification
ZNEO
Option Bit
locations
locations
locations
locations
CFh
On-Chip Debugger
—
—
.
Z16F Series
314