Z16F3211FI20SG Zilog, Z16F3211FI20SG Datasheet - Page 305

IC ZNEO MCU FLASH 32K 80QFP

Z16F3211FI20SG

Manufacturer Part Number
Z16F3211FI20SG
Description
IC ZNEO MCU FLASH 32K 80QFP
Manufacturer
Zilog
Series
Encore!® ZNEOr
Datasheet

Specifications of Z16F3211FI20SG

Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
60
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
80-BQFP
Processor Series
Z16F3x
Core
Zneo
Data Bus Width
16 bit
Data Ram Size
2 B
Interface Type
ESPI, I2C, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
60
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z16F2800100ZCOG
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 12 Channel
For Use With
770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
269-4569

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z16F3211FI20SG
Manufacturer:
Zilog
Quantity:
131
Part Number:
Z16F3211FI20SG
Manufacturer:
Zilog
Quantity:
10 000
Table 153. DMA X Source Address Register High (DMAxSARH)
Table 154. DMA X Source Address Register Low (DMAxSARL)
Table 155. DMA X List Address Register Upper DMAxLARU
PS022008-0810
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
DMA List Address Register
R/W
R/W
R/W
7
0
7
0
7
0
This registers is written when the list mode for the DMA is used. This register contains the
address of the current list the DMA is operating on. Writing the DMAxLARL register
enables the DMA for list operation.
In direct mode this register is used to set a watermark interrupt. This interrupt occurs when
the DMATXLN[15:8] equals 0 and DMAxTXLN[7:0] equals DMAxLARU. Note when
using the watermark the DMAxLARL must not be written.
R/W
R/W
R/W
6
0
6
0
6
0
FFE41DH, FFE42DH, FFE43DH, FFE44DH
FFE41AH, FFE42AH, FFE43AH, FFE44AH
FFE41BH, FFE42BH, FFE43BH, FFE44BH
R/W
R/W
R/W
5
5
5
0
0
0
P R E L I M I N A R Y
R/W
R/W
R/W
4
0
4
0
4
0
DMAxSARH
DMAxLARU
DMAxSARL
R/W
R/W
R/W
3
3
3
0
0
0
R/W
R/W
R/W
2
0
2
0
2
0
Product Specification
ZNEO
R/W
R/W
R/W
1
1
1
0
0
0
DMA Controller
Z16F Series
R/W
R/W
R/W
0
0
0
0
0
0
289

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