Z16F3211FI20SG Zilog, Z16F3211FI20SG Datasheet - Page 292

• Manufacturer Part Number: Z16F3211FI20SG
• Description: IC ZNEO MCU FLASH 32K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F3211FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F3x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 2 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4569

PS022008-0810
Direct DMA Setup and Operation
Follows the steps below to setup the DMA in direct mode:
1. Write the
2. Write the DMAxDAR register with the destination address.
3. Write the DMAxSAR register with the source address.
4. Write the DMAxTXLN with the transfer length.
5. Write DMAxLARU with water mark if required, otherwise write to zero.
6. Write DMAxCTL. Note that control register and address are directly written with
7. The DMA is now set up and begins operating when it receives a request.
Once the DMA is set up and a request is received the DMA does the following:
1. Generate a request to the CPU.
2. It transfers data for each request until the transfer length reaches zero or the DMA
3. When the DMA receives the Request EOF signal, or the transfer length reaches zero it
word and quad operations.
–
–
–
–
–
–
–
–
–
–
receives a Request EOF signal.
resets the
If
CMDSTAT field of the DMAxCTL register. If the
with a Request EOF the DMA channel generates a request to the CPU.
If
CPU.
EOF
EOF
DMAxEN, set to one.
LOOP, reset to zero, not used in this mode
TXSIZE, set to the transfer size, byte, word or quad.
DSTCTL, set to fixed, increment, or decrement.
SRCCTL, set to fixed, increment, or decrement.
IEOB, set to one to generate an interrupt at the end of buffer or water mark.
TXFR, reset to zero, not used in this mode.
EOF, set this bit to one if this is an EOF buffer.
HALT, reset to zero, not used in this mode.
CMDSTAT, set these bits with the command for the peripheral.
is set then the DMA reads the status from the peripheral and places it in the
is not set and
DAMxREQSEL
DMAxEN
bit and then does the following based upon the
IEOB
P R E L I M I N A R Y
to select the request source.
is set then the DMA channel generates a request to the
IEOB
bit is set or the buffer ended
Product Specification
ZNEO
EOF
DMA Controller
and
Z16F Series
IEOB
bits.
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