MC908JB8JDWE Freescale Semiconductor, MC908JB8JDWE Datasheet - Page 106

• Manufacturer Part Number: MC908JB8JDWE
• Description: IC MCU 8K FLASH 3MHZ 20-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JB8JDWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: USB
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: HC08JB
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: USB
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Controller Family/series: HC08
• No. Of I/o's: 13
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

System Integration Module (SIM)
Technical Data
106
INTERRUPT
INTERRUPT
MODULE
MODULE
I BIT
I BIT
R/W
R/W
IAB
IDB
IAB
IDB
DUMMY
DUMMY
Interrupts are latched and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt can take precedence, regardless of priority,
until the latched interrupt is serviced or the I bit is cleared.
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume.
8-10
SP – 4
SP
PC – 1[7:0] PC – 1[15:8]
shows interrupt recovery timing.
CCR
Figure 8-10. Interrupt Recovery
SP – 3
SP – 1
Figure 8-9. Interrupt Entry
System Integration Module (SIM)
A
SP – 2
SP – 2
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
X
X
Figure 8-9
SP – 3
SP – 1
PC –1 [15:8] PC – 1[7:0]
A
SP – 4
SP
shows interrupt entry timing.
CCR
VECT H
PC
V DATA H
OPCODE
VECT L
PC + 1
OPERAND
V DATA L
Freescale Semiconductor
START ADDR
OPCODE
Figure