MC908JB8JDWE Freescale Semiconductor, MC908JB8JDWE Datasheet - Page 20

• Manufacturer Part Number: MC908JB8JDWE
• Description: IC MCU 8K FLASH 3MHZ 20-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JB8JDWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: USB
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: HC08JB
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: USB
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Controller Family/series: HC08
• No. Of I/o's: 13
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

List of Figures
Technical Data
20
Figure
8-4
8-5
8-6
8-7
8-8
8-9
8-10 Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
8-11 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . 107
8-12 Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . . 109
8-13 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
8-14 Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . . 111
8-15 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . . 111
8-16 Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
8-17 Stop Mode Recovery from Interrupt or Break . . . . . . . . . . . . . 113
8-18 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . 113
8-19 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . 115
8-20 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . 116
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10 Regulator Electrical Connections . . . . . . . . . . . . . . . . . . . . . . 133
9-11 Receiver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
9-12 Differential Input Sensitivity Range. . . . . . . . . . . . . . . . . . . . . 135
9-13 Data Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
9-14 Data Signal Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . .136
9-15 USB Address Register (UADDR) . . . . . . . . . . . . . . . . . . . . . . 138
9-16 USB Interrupt Register 0 (UIR0) . . . . . . . . . . . . . . . . . . . . . . . 139
9-17 USB Interrupt Register 1 (UIR1) . . . . . . . . . . . . . . . . . . . . . . . 141
9-18 USB Interrupt Register 2 (UIR2) . . . . . . . . . . . . . . . . . . . . . . . 144
External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Interrupt Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
USB I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 120
USB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Supported Transaction Types Per Endpoint. . . . . . . . . . . . . . 125
Supported USB Packet Types . . . . . . . . . . . . . . . . . . . . . . . . 126
Sync Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
SOP, Sync Signaling, and Voltage Levels . . . . . . . . . . . . . . . 127
EOP Transaction Voltage Levels . . . . . . . . . . . . . . . . . . . . . . 129
EOP Width Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
External Low-Speed Device Configuration . . . . . . . . . . . . . . . 132
List of Figures
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
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Freescale Semiconductor
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