MC908JB8JDWE Freescale Semiconductor, MC908JB8JDWE Datasheet - Page 215

• Manufacturer Part Number: MC908JB8JDWE
• Description: IC MCU 8K FLASH 3MHZ 20-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JB8JDWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: USB
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: HC08JB
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: USB
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Controller Family/series: HC08
• No. Of I/o's: 13
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.7.2 Data Direction Register E
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
NOTE:
NOTE:
Address:
Data direction register E determines whether each port E pin is an input
or an output. Writing a logic 1 to a DDRE bit enables the output buffer for
the corresponding port E pin; a logic 0 disables the output buffer.
DDRE[4:0] — Data Direction Register E Bits
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
For those devices packaged in a 20-pin PDIP and 20-pin SOIC package,
PTE2 and PTE0 are not connected. DDRE2 and DDRE0 should be set
to a 1 to configure PTE2 and PTE0 as outputs.
Figure 12-16
Reset:
Read:
Write:
These read/write bits control port E data direction. Reset clears
DDRE[4:0], configuring all port E pins as inputs.
PTE4 and PTE3 pins are open-drain when configured as output.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
$0009
Bit 7
Figure 12-15. Data Direction Register E (DDRE)
0
0
shows the port E I/O circuit logic.
Input/Output Ports (I/O)
= Unimplemented
6
0
0
0
5
0
DDRE4
0
4
DDRE3
3
0
DDRE2
2
0
Input/Output Ports (I/O)
DDRE1
1
0
Technical Data
DDRE0
Bit 0
Port E
0
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