MC908JB8ADWE Freescale Semiconductor, MC908JB8ADWE Datasheet - Page 111

• Manufacturer Part Number: MC908JB8ADWE
• Description: IC MCU 3MHZ 8K FLASH 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JB8ADWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: USB
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: HC08JB
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: USB
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 5.25 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Wait mode can also be exited by a reset or break. A break interrupt
during wait mode sets the SIM break stop/wait bit, SBSW, in the break
status register (BSR). If the COP disable bit, COPD, in the mask option
register is logic 0, then the computer operating properly module (COP)
is enabled and remains active in wait mode.
Figure 8-14
OSCXCLK
IAB
IDB
NOTE: EXITSTOPWAIT = RST pin or CPU interrupt or break interrupt
EXITSTOPWAIT
R/W
IAB
IDB
NOTE: Previous data can be operand data or the WAIT opcode, depending on the
RST
IDB
IAB
Figure 8-14. Wait Recovery from Interrupt or Break
$A6
System Integration Module (SIM)
$A6
Figure 8-15. Wait Recovery from Internal Reset
last instruction.
WAIT ADDR
and
$6E0B
$A6
$6E0B
$A6
Figure 8-13. Wait Mode Entry Timing
PREVIOUS DATA
Figure 8-15
$A6
$A6
WAIT ADDR + 1
$6E0C
CYCLES
$01
show the timing for WAIT recovery.
32
NEXT OPCODE
$00FF
$0B
CYCLES
32
$00FE
SAME
System Integration Module (SIM)
$6E
$00FD
SAME
RST VCT H RST VCT L
Low-Power Modes
SAME
$00FC
Technical Data
SAME
111