MC908JB8ADWE Freescale Semiconductor, MC908JB8ADWE Datasheet - Page 241

• Manufacturer Part Number: MC908JB8ADWE
• Description: IC MCU 3MHZ 8K FLASH 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JB8ADWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: USB
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: HC08JB
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: USB
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 5.25 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.5 COP Control Register
15.6 Interrupts
15.7 Monitor Mode
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Address:
Reset:
COPRS — COP Rate Select Bit
COPD — COP Disable Bit
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
The COP does not generate CPU interrupt requests.
The COP is disabled in monitor mode when V
IRQ pin or on the RST pin.
Read:
Write:
COPRS selects the COP timeout period. Reset clears COPRS.
COPD disables the COP module.
1 = COP timeout period is (2
0 = COP timeout period is (2
1 = COP module disabled
0 = COP module enabled
$FFFF
Bit 7
Computer Operating Properly (COP)
Figure 15-3. COP Control Register (COPCTL)
6
5
Low byte of reset vector
Clear COP counter
Unaffected by reset
4
13
18
– 2
– 2
4
4
Computer Operating Properly (COP)
) × OSCXOUT cycles
) × OSCXOUT cycles
3
DD
+ V
2
HI
COP Control Register
is present on the
1
Technical Data
Bit 0
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