R5F21244SNFP#U0 Renesas Electronics America, R5F21244SNFP#U0 Datasheet

IC R8C MCU FLASH 16K 52LQFP

R5F21244SNFP#U0

Manufacturer Part Number
R5F21244SNFP#U0
Description
IC R8C MCU FLASH 16K 52LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/R8C/Tiny/24r
Datasheets

Specifications of R5F21244SNFP#U0

Core Processor
R8C
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
52-LQFP
For Use With
R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
To our customers,
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
On April 1
st
, 2010, NEC Electronics Corporation merged with Renesas Technology
Renesas Electronics website:
Old Company Name in Catalogs and Other Documents
http://www.renesas.com
April 1
Renesas Electronics Corporation
st
, 2010

Related parts for R5F21244SNFP#U0

R5F21244SNFP#U0 Summary of contents

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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...

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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...

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R8C/Tiny Series 16 Software Manual RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER Rev.2.00 2005.10 ...

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Keep safety first in your circuit designs! Renesas Technology Corp. puts the maximum effort into making semiconductor products 1. better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...

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This software manual is written for the R8C/Tiny Series. It applies to all microcomputers integrating the R8C/Tiny Series CPU core. The reader of this manual is assumed to have a basic knowledge of electrical circuits, logic circuits, and microcomputers. This ...

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M16C Family Documents The following documents were prepared for the M16C family. Document Short Sheet Data Sheet Hardware Manual Software Manual Application Note RENESAS TECHNICAL UPDATE NOTES: 1. Before using this material, please visit the our website to verify that ...

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Chapter 1 Overview ___________________________________________________ 1.1 Features of R8C/Tiny Series ...................................................................................................... 2 1.1.1 Features of R8C/Tiny Series .............................................................................................. 2 1.1.2 Speed Performance ............................................................................................................ 2 1.2 Address Space ........................................................................................................................... 3 1.3 Register Configuration ................................................................................................................ 4 1.3.1 Data registers (R0, R0H, R0L, R1, ...

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Data Arrangement .................................................................................................................... 16 1.8.1 Data Arrangement in Register .......................................................................................... 16 1.8.2 Data Arrangement in Memory ........................................................................................... 17 1.9 Instruction Formats ................................................................................................................... 18 1.9.1 Generic Format (:G) .......................................................................................................... 18 1.9.2 Quick Format (:Q) ............................................................................................................. 18 1.9.3 Short Format (:S) ...

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Interrupt Control ...................................................................................................................... 249 5.2.1 I Flag ...............................................................................................................................249 5.2.2 IR Bit ...............................................................................................................................249 5.2.3 ILVL2 to ILVL0 bis, IPL ................................................................................................... 250 5.2.4 Changing Interrupt Control Register ............................................................................... 251 5.3 Interrupt Sequence .................................................................................................................252 5.3.1 Interrupt Response Time ................................................................................................ 253 5.3.2 Changes ...

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Quick Reference in Alphabetic Order Page No. for Mnemonic Function ABS 39 ADC 40 ADCF 41 ADD 42 ADJNZ 44 AND 45 BAND 47 BCLR 48 BMCnd 49 BMEQ/Z 49 BMGE 49 BMGEU/C 49 BMGT 49 BMGTU 49 BMLE 49 ...

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Quick Reference in Alphabetic Order Page No. for Mnemonic Function Dir MOV 93 MOVHH 93 MOVHL 93 MOVLH 93 MOVLL 93 MUL 94 MULU 95 NEG 96 NOP 97 NOT POP 101 POPC 102 POPM 103 PUSH ...

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Quick Reference by Function Function Mnemonic Transfer MOV MOVA MOVDir POP POPM PUSH PUSHA PUSHM LDE STE STNZ STZ STZX XCHG Bit BAND manipulation BCLR Cnd BM BNAND BNOR BNOT BNTST BNXOR BOR BSET BTST BTSTC BTSTS BXOR Shift ROLC ...

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Quick Reference by Function Function Mnemonic Arithmetic DADD DEC DIV DIVU DIVX DSBB DSUB EXTS INC MUL MULU NEG RMPA SBB SUB Logical AND NOT OR TST XOR Jump ADJNZ SBJNZ JCnd JMP JMPI JSR JSRI RTS String SMOVB SMOVF ...

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Quick Reference by Function Function Mnemonic Other LDIPL NOP POPC PUSHC REIT STC STCTX UND WAIT Description Set interrupt enable level No operation Restore control register Save control register Return from interrupt Transfer from control register Save context Interrupt for ...

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Quick Reference by Addressing Mode (General Instruction Addressing) Mnemonic ABS ADC ADCF *1 ADD *1 ADJNZ AND CMP DADC DADD DEC DIV DIVU DIVX DSBB DSUB ENTER *2 EXTS *3 *4 INC INT *1 JMPI *1 JSRI *1 LDC *1 ...

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Quick Reference by Addressing Mode (General Instruction Addressing) Mnemonic *1 MOV MOVA Dir MOV MUL MULU NEG NOT OR POP *1 POPM PUSH PUSHA *1 PUSHM ROLC RORC ROT SBB *1 SBJNZ *1 SHA *1 SHL *1 STC *1 STCTX ...

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Quick Reference by Addressing Mode (General Instruction Addressing) Mnemonic STZX SUB TST XCHG XOR Addressing Mode Quick Reference-8 Page No. for Page No. for Function Instruction Code /No. of Cycles 126 236 127 236 129 239 132 242 133 243 ...

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Quick Reference by Addressing Mode (Special Instruction Addressing) Mnemonic *1 ADD *1 ADJNZ JCnd JMP *1 JMPI JSR *1 JSRI *1 LDC LDCTX *1 LDE LDINTB *1 MOV POPC *1 POPM PUSHC *1 PUSHM *1 SBJNZ *1 SHA *1 SHL ...

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Quick Reference by Addressing Mode (Bit Instruction Addressing) Addressing Mode Mnemonic BAND BCLR Cnd BM BNAND BNOR BNOT BNTST BNXOR BOR BSET BTST BTSTC BTSTS BXOR FCLR FSET Page No. for Function ...

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This page intentionally left blank. Quick Reference-11 ...

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Features of R8C/Tiny Series 1.2 Address Space 1.3 Register Configuration 1.4 Flag Register (FLG) 1.5 Register Banks 1.6 Internal State after Reset is Cleared 1.7 Data Types 1.8 Data Arrangement 1.9 Instruction Formats 1.10 Vector Tables Chapter 1 Overview ...

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Chapter 1 Overview 1.1 Features of R8C/Tiny Series The R8C/Tiny Series of single-chip microcomputers was developed for embedded applications. The R8C/Tiny Series supports instructions tailored for the C language, with frequently used instructions implemented in one-byte op-code. It thus allows ...

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Chapter 1 Overview 1.2 Address Space Figure 1.2.1 shows the address space. Addresses 00000 through 002FF 16 the R8C/Tiny Series, the SFR area extends from 002FF Addresses from 00400 and below make up the memory area. In some models in ...

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Chapter 1 Overview 1.3 Register Configuration The central processing unit (CPU) contains the 13 registers shown in figure 1.3.1. Of these registers, R0, R1, R2, R3, A0, A1, and FB each consist of two sets of registers configured as two ...

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Chapter 1 Overview 1.3.2 Address Registers (A0 and A1) The address registers (A0 and A1) are 16-bit registers with functions similar to those of the data regis- ters. These registers are used for address register-based indirect addressing and address register- ...

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Chapter 1 Overview 1.4 Flag Register (FLG) Figure 1.4.1 shows the configuration of the flag register (FLG). The function of each flag is described below. 1.4.1 Bit 0: Carry Flag (C Flag) This flag holds bits carried, borrowed, or shifted-out ...

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Chapter 1 Overview 1.4.10 Bits 12 to 14: Processor Interrupt Priority Level (IPL) The processor interrupt priority level (IPL) consists of three bits, enabling specification of eight proces- sor interrupt priority levels from level 0 to level ...

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Chapter 1 Overview 1.5 Register Banks The R8C/Tiny has two register banks, each comprising data registers (R0, R1, R2, and R3), address regis- ters (A0 and A1), and a frame base register (FB). These two register banks are switched by ...

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Chapter 1 Overview 1.6 Internal State after Reset is Cleared The contents of each register after a reset is cleared are as follows. • Data registers (R0, R1, R2, and R3): 0000 • Address registers (A0 and A1): 0000 • ...

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Chapter 1 Overview 1.7 Data Types There are four data types: integer, decimal, bit, and string. 1.7.1 Integer An integer can be signed or unsigned. A negative value of a signed integer is represented by two’s complement. Signed byte (8 ...

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Chapter 1 Overview 1.7.2 Decimal The decimal data type is used by the DADC, DADD, DSBB, and DSUB instructions. Pack format (2 digits) Pack format (4 digits) Figure 1.7.2 Decimal Data Rev.2.00 Oct 17, 2005 page 11 of 263 REJ09B0001-0200 ...

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Chapter 1 Overview 1.7.3 Bits Register bits Figure 1.7.3 shows register bit specification. Register bits can be specified by register directly (bit bit, An). Use bit specify a bit in a data register (Rn); use bit, ...

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Chapter 1 Overview (1) Bit Specification by Bit, Base Figure 1.7.5 shows the relationship between the memory map and the bit map. Memory bits can be handled as an array of consecutive bits. Bits can be specified by a combination ...

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Chapter 1 Overview (2) SB/FB Relative Bit Specification For SB/FB-based relative addressing, use bit 0 of the address that is the sum of the address set in static base register (SB) or frame base register (FB) plus the address set ...

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Chapter 1 Overview 1.7.4 String String data consists of a given length of consecutive byte (8-bit) or word (16-bit) data. This data type can be used in three string instructions: character string backward transfer (SMOVB instruction), character string forward transfer ...

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Chapter 1 Overview 1.8 Data Arrangement 1.8.1 Data Arrangement in Register Figure 1.8.1 shows the relationship between a register’s data size and bit numbers. Nibble (4-bit) data Byte (8-bit) data Word (16-bit) data Long word (32-bit) data Figure 1.8.1 Data ...

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Chapter 1 Overview 1.8.2 Data Arrangement in Memory Figure 1.8.2 shows the data arrangement in memory. Figure 1.8.3 shows some operation examples. N N+1 N+2 N+3 Byte (8-bit) data N N+1 N+2 N+3 20-bit (Address) data Figure 1.8.2 Data Arrangement ...

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Chapter 1 Overview 1.9 Instruction Formats The instruction formats can be classified into four types: generic, quick, short, and zero. The number of instruction bytes that can be chosen by a given format is least for the zero format, and ...

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Chapter 1 Overview 1.10 Vector Tables Interrupt vector tables are the only vector tables. There are two types of interrupt vector tables: fixed and variable. 1.10.1 Fixed Vector Tables A fixed vector table is an address-fixed vector table. Part of ...

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Chapter 1 Overview 1.10.2 Variable Vector Tables A variable vector table is an address-variable vector table. Specifically, this type of vector table is a 256- byte interrupt vector table that uses the value indicated by the interrupt table register (INTB) ...

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Addressing Modes 2.1 Addressing Modes 2.2 Guide to This Chapter 2.3 General Instruction Addressing 2.4 Special Instruction Addressing 2.5 Bit Instruction Addressing Chapter 2 ...

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Chapter 2 Addressing Modes 2.1 Addressing Modes This section describes the symbols used to represent addressing modes and operations of each address- ing mode. The R8C/Tiny Series has three types of addressing modes as outlined below. 2.1.1 General Instruction Addressing ...

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Chapter 2 Addressing Modes 2.2 Guide to This Chapter An example illustrating how to read this chapter is shown below. (1) Address register relative The value indicated by the displace- dsp:8[A0] ment (dsp) plus the content of the (2) dsp:8[A1] ...

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Chapter 2 Addressing Modes 2.3 General Instruction Addressing Immediate The immediate data indicated by #IMM #IMM is the object of the operation. #IMM8 #IMM16 #IMM20 Register direct The specified register is the object of R0L the operation. R0H R1L R1H ...

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Chapter 2 Addressing Modes Address register relative The value indicated by the displace- dsp:8[A0] ment (dsp) plus the content of the dsp:8[A1] address register (A0/A1)—added dsp:16[A0] without the sign bits—is the effective address for the operation. dsp:16[A1] However, if the ...

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Chapter 2 Addressing Modes Stack pointer relative dsp:8[SP] The address indicated by the content of the stack pointer (SP) plus the value indicated by the displacement (dsp)—added including the sign bits—is the effective address for the operation. The stack pointer ...

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Chapter 2 Addressing Modes 2.4 Special Instruction Addressing 20-bit absolute The value indicated by abs20 is the abs20 effective address for the operation. The effective address range is 00000 FFFFF . 16 This addressing mode can be used with the ...

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Chapter 2 Addressing Modes 32-bit register direct The 32-bit concatenated register content of two R2R0 specified registers is the object of the operation. R3R1 A1A0 This addressing mode can be used with the SHL, SHA, JMPI, and JSRI instructions. Valid ...

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Chapter 2 Addressing Modes Program counter relative • If the jump length specifier (.length) label is (.S), the base address plus the value indicated by the displacement (dsp)—added without the sign bits—is the effective address. This addressing mode can be ...

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Chapter 2 Addressing Modes 2.5. Bit Instruction Addressing This addressing mode type can be used with the following instructions: BCLR, BSET, BNOT, BTST, BNTST, BAND, BNAND, BOR, BNOR, BXOR, BNXOR, BM Register direct The specified register bit is the object ...

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Chapter 2 Addressing Modes Address register relative base:8[A0] The bit that is the number of bits base:8[A1] indicated by the address register base:16[A0] (A0/A1) away from bit 0 at the address indicated by base is the base:16[A1] object of the ...

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Chapter 2 Addressing Modes FB relative The bit that is the number of bits bit,base:8[FB] indicated by bit away from bit 0 at the address indicated by the frame base register (FB) plus the value indicated by base (added including ...

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Guide to This Chapter 3.2 Functions Chapter 3 Functions ...

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Chapter 3 Functions 3.1 Guide to This Chapter In this chapter each instruction’s syntax, operation, function, selectable src/dest, and flag changes are listed, and description examples and related instructions are shown. An example illustrating how to read this chapter is ...

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Chapter 3 Functions (1) Mnemonic The mnemonic explained in the page. (2) Instruction Code/Number of Cycles The page on which the instruction code and number of cycles is listed. Refer to this page for information on the instruction code and ...

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Chapter 3 Functions Chapter 3 Functions MOV (1) (2) [ Syntax ] (3) MOV.size (:format) src,dest (4) [ Operation ] dest src [ Function ] (5) • This instruction transfers dest • and the selected ...

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Chapter 3 Functions (4) Operation Explains the operation of the instruction using symbols. (5) Function Explains the function of the instruction and precautions to be taken when using the instruction. (6) Selectable src / dest (label) If the instruction has ...

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Chapter 3 Functions The syntax of the jump instructions JMP, JPMI, JSR, and JSRI are illustrated below by example . Chapter 3 Functions JMP (1) (2) [ Syntax ] (3) JMP (.length) label (3) Syntax Indicates the instruction syntax using ...

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Chapter 3 Functions ABS [ Syntax ] ABS.size dest [ Operation ] dest dest [ Function ] • This instruction takes the absolute value of [ Selectable dest ] [ Flag Change ] Flag Change ...

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Chapter 3 Functions ADC [ Syntax ] ADC.size src,dest [ Operation ] dest src + dest + [ Function ] dest • This instruction adds dest • and the selected size specifier (.size) is (.B), ...

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Chapter 3 Functions ADCF [ Syntax ] ADCF.size dest [ Operation ] dest dest + C [ Function ] dest This instruction adds [ Selectable dest ] [ Flag Change ] Flag Change Conditions O ...

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Chapter 3 Functions ADD [ Syntax ] ADD.size (:format) src,dest [ Operation ] dest dest + src [ Function ] dest • This instruction adds dest • and the selected size specifier (.size) is (.B), ...

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Chapter 3 Functions [src/dest Classified by Format] G format src R0L/R0 R0H/R1 R1L/R2 A0/A0 *1 A1/A1 *1 [A0] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:16[A0] dsp:16[A1] dsp:16[SB] dsp:20[A0] dsp:20[A1] abs20 R2R0 R3R1 A1A0 *1 If (.B) is selected as the size specifier (.size), ...

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Chapter 3 Functions ADJNZ [ Syntax ] ADJNZ.size src,dest,label [ Operation ] dest dest + src if dest 0 then jump label [ Function ] dest • This instruction adds • If the addition results in any value other than ...

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Chapter 3 Functions AND [ Syntax ] AND.size (:format) src,dest [ Operation ] dest src dest [ Function ] • This instruction logically ANDs dest • and the selected size specifier (.size) is (.B), src ...

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Chapter 3 Functions [src/dest Classified by Format] G format src R0L/R0 R0H/R1 R1L/R2 A0/A0 *1 A1/A1 *1 [A0] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:16[A0] dsp:16[A1] dsp:16[SB] dsp:20[A0] dsp:20[A1] abs20 R2R0 R3R1 A1A0 *1 If (.B) is selected as the size specifier (.size), ...

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Chapter 3 Functions BAND [ Syntax ] BAND src [ Operation ] C src C [ Function ] • This instruction logically ANDs the C flag and [ Selectable src ] src bit,R0 bit,R1 bit,R2 bit,A0 bit,A1 [A0] base:8[A0] base:8[A1] ...

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Chapter 3 Functions BCLR [ Syntax ] BCLR (:format) dest [ Operation ] dest 0 [ Function ] • This instruction stores Selectable dest ] [ Flag Change ] Flag Change [ ...

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Chapter 3 Functions BM Cnd [ Syntax ] BM Cnd dest [ Operation ] if true then dest 1 else dest 0 [ Function ] • This instruction transfers the true or false value of the condition indicated by condition ...

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Chapter 3 Functions BNAND [ Syntax ] BNAND src [ Operation ] ______ C src C [ Function ] • This instruction logically ANDs the C flag and the inverted value of flag. [ Selectable src ] src bit,R0 bit,R1 ...

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Chapter 3 Functions BNOR [ Syntax ] BNOR src [ Operation ] ______ C src C [ Function ] • This instruction logically ORs the C flag and the inverted value of flag. [ Selectable src ] src bit,R0 bit,R1 ...

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Chapter 3 Functions BNOT [ Syntax ] BNOT(:format) dest [ Operation ] ________ dest dest [ Function ] dest • This instruction inverts [ Selectable dest ] [ Flag Change ] Flag Change [ Description ...

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Chapter 3 Functions BNTST [ Syntax ] BNTST src [ Operation ] Z src ______ C src [ Function ] • This instruction transfers the inverted value of flag. [ Selectable src ] src bit,R0 bit,R1 bit,R2 bit,A0 bit,A1 [A0] ...

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Chapter 3 Functions BNXOR [ Syntax ] BNXOR src [ Operation ] ______ A C src C [ Function ] • This instruction exclusive ORs the C flag and the inverted value of flag. [ Selectable src ] src bit,R0 ...

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Chapter 3 Functions BOR [ Syntax ] BOR src [ Operation ] C src C [ Function ] • This instruction logically ORs the C flag and [ Selectable src ] src bit,R0 bit,R1 bit,R2 bit,A0 bit,A1 [A0] base:8[A0] base:8[A1] ...

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Chapter 3 Functions BRK [ Syntax ] BRK [ Operation ] SP SP – 2 M(SP) ( – 2 M(SP) ( M(FFFE4 ) 16 [ Function ] • This instruction generates ...

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Chapter 3 Functions BSET [ Syntax ] BSET (:format) dest [ Operation ] dest 1 [ Function ] • This instruction stores Selectable dest ] [ Flag Change ] Flag Change [ ...

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Chapter 3 Functions BTST [ Syntax ] BTST (:format) src [ Operation ] ______ Z src C src [ Function ] • This instruction transfers the inverted value of the C flag. [ Selectable src ] src bit,R0 bit,R1 bit,R2 ...

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Chapter 3 Functions BTSTC [ Syntax ] BTSTC dest [ Operation ] ________ Z dest C dest dest 0 [ Function ] • This instruction transfers the inverted value of dest to the C flag. Then it stores 0 in ...

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Chapter 3 Functions BTSTS [ Syntax ] BTSTS dest [ Operation ] ________ Z dest C dest dest 1 [ Function ] • This instruction transfers the inverted value of the C flag. Then it stores Selectable ...

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Chapter 3 Functions BXOR [ Syntax ] BXOR src [ Operation ] A C src C [ Function ] • This instruction exclusive ORs the C flag and [ Selectable src ] src bit,R0 bit,R1 bit,R2 bit,A0 bit,A1 [A0] base:8[A0] ...

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Chapter 3 Functions CMP [ Syntax ] CMP.size (:format) src,dest [ Operation ] dest – src [ Function ] • Flag bits in the flag register change depending on the result of subtraction of dest • ...

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Chapter 3 Functions [src/dest Classified by Format] G format src R0L/R0 R0H/R1 R1L/R2 A0/A0 *1 A1/A1 *1 [A0] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:16[A0] dsp:16[A1] dsp:16[SB] dsp:20[A0] dsp:20[A1] abs20 R2R0 R3R1 A1A0 *1 If (.B) is selected as the size specifier (.size), ...

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Chapter 3 Functions DADC [ Syntax ] DADC.size src,dest [ Operation ] dest src + dest + [ Function ] dest • This instruction adds [ Selectable src/dest ] src R0L/R0 R0H/R1 R1L/R2 A0/A0 A1/A1 [A0] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:16[A0] ...

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Chapter 3 Functions DADD [ Syntax ] DADD.size src,dest [ Operation ] dest src + dest [ Function ] dest • This instruction adds [ Selectable src/dest ] src R0L/R0 R0H/R1 R1L/R2 A0/A0 A1/A1 [A0] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:16[A0] dsp:16[A1] ...

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Chapter 3 Functions DEC [ Syntax ] DEC.size dest [ Operation ] dest dest – Function ] • This instruction decrements [ Selectable dest ] [ Flag Change ] Flag Change Conditions S ...

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Chapter 3 Functions DIV [ Syntax ] DIV.size src [ Operation ] If the size specifier (.size) is (.B) R0L (quotient), R0H (remainder) If the size specifier (.size) is (.W) R0 (quotient), R2 (remainder) [ Function ] • This instruction ...

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Chapter 3 Functions DIVU [ Syntax ] DIVU.size src [ Operation ] If the size specifier (.size) is (.B) R0L (quotient), R0H (remainder) If the size specifier (.size) is (.W) R0 (quotient), R2 (remainder) [ Function ] • This instruction ...

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Chapter 3 Functions DIVX [ Syntax ] DIVX.size src [ Operation ] If the size specifier (.size) is (.B) R0L (quotient), R0H (remainder) If the size specifier (.size) is (.W) R0 (quotient), R2 (remainder) [ Function ] • This instruction ...

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Chapter 3 Functions DSBB [ Syntax ] DSBB.size src,dest [ Operation ] dest dest – src – [ Function ] • This instruction subtracts dest stores the result Selectable src/dest ] src R0L/R0 R0H/R1 R1L/R2 A0/A0 A1/A1 ...

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Chapter 3 Functions DSUB [ Syntax ] DSUB.size src,dest [ Operation ] dest dest – src [ Function ] • This instruction subtracts [ Selectable src/dest ] src R0L/R0 R0H/R1 R1L/R2 A0/A0 A1/A1 [A0] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:16[A0] dsp:16[A1] dsp:16[SB] ...

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Chapter 3 Functions ENTER [ Syntax ] ENTER src [ Operation ] SP SP – M(SP – [ Function ] • This instruction generates a stack frame. • The diagrams below show the stack area ...

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Chapter 3 Functions EXITD [ Syntax ] EXITD [ Operation ] M(SP M(SP M(SP Function ] • This instruction deallocates a stack frame ...

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Chapter 3 Functions EXTS [ Syntax ] EXTS.size dest [ Operation ] dest EXT(dest) [ Function ] • This instruction sign extends • If (.B) is selected as the size specifier (.size), • If (.W) is selected as the size ...

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Chapter 3 Functions FCLR [ Syntax ] FCLR dest [ Operation ] dest 0 [ Function ] • This instruction stores Selectable dest ] [ Flag Change ] Flag Change *1 *1 ...

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Chapter 3 Functions FSET [ Syntax ] FSET dest [ Operation ] dest 1 [ Function ] • This instruction stores Selectable dest ] [ Flag Change ] Flag Change *1 *1 ...

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Chapter 3 Functions INC [ Syntax ] INC.size dest [ Operation ] dest dest + 1 [ Function ] • This instruction adds Selectable dest ] [ Flag Change ] Flag Change ...

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Chapter 3 Functions INT [ Syntax ] INT src [ Operation ] SP SP – 2 M(SP) ( – 2 M(SP) ( M(IntBase + [ Function ] • This instruction generates ...

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Chapter 3 Functions INTO [ Syntax ] INTO [ Operation ] SP SP – 2 M(SP) ( – 2 M(SP) ( M(FFFE0 ) 16 [ Function ] • If the O ...

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Chapter 3 Functions J Cnd [ Syntax ] J Cnd label [ Operation ] if true then jump label [ Function ] • This instruction causes program flow to branch after checking the execution result of the preceding instruction against ...

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Chapter 3 Functions JMP [ Syntax ] JMP(.length) label [ Operation ] PC label [ Function ] • This instruction causes control to jump to label. [ Selectable label ] .length label * label ...

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Chapter 3 Functions JMPI [ Syntax ] JMPI.length src [ Operation ] When jump distance specifier (.length src [ Function ] • This instruction causes control to jump to the address indicated by memory, specify the ...

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Chapter 3 Functions JSR [ Syntax ] JSR(.length) label [ Operation ] SP SP – M(SP) ( – M(SP) ( label *1 n denotes the number of instruction bytes. [ Function ] • This instruction ...

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Chapter 3 Functions JSRI [ Syntax ] JSRI.length src [ Operation ] When jump distance specifier (.length – 1 M(SP) ( – 2 M(SP) ( src *1 n ...

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Chapter 3 Functions LDC [ Syntax ] LDC src,dest [ Operation ] dest src [ Function ] • This instruction transfers memory, the required memory capacity is 2 bytes. • If the destination is INTBL or INTBH, make sure that ...

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Chapter 3 Functions LDCTX [ Syntax ] LDCTX abs16,abs20 [ Function ] • This instruction restores task context from the stack area. • Set the RAM address that contains the task number in abs16 and the start address of table ...

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Chapter 3 Functions LDE [ Syntax ] LDE.size src,dest [ Operation ] dest src [ Function ] • This instruction transfers dest • and the selected size specifier (.size) is (.B bits. [ ...

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Chapter 3 Functions LDINTB [ Syntax ] LDINTB src [ Operation ] INTBHL src [ Function ] • This instruction transfers • The LDINTB instruction is a macro-instruction consisting of the following: LDC LDC [ Selectable src ] src #IMM20 ...

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Chapter 3 Functions LDIPL [ Syntax ] LDIPL src [ Operation ] IPL src [ Function ] • This instruction transfers [ Selectable src ] src #IMM *1 *1 The acceptable range of values is 0 < #IMM < 7 ...

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Chapter 3 Functions MOV [ Syntax ] MOV.size (:format) src,dest [ Operation ] dest src [ Function ] • This instruction transfers dest • and the selected size specifier (.size) is (.B), src in 16 ...

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Chapter 3 Functions [src/dest Classified by Format] G format src R0L/R0 R0H/R1 R1L/R2 A0/A0 *1 A1/A1 *1 [A0] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:16[A0] dsp:16[A1] dsp:16[SB] dsp:20[A0] dsp:20[A1] abs20 R2R0 R3R1 A1A0 *1 If (.B) is selected as the size specifier (.size), ...

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Chapter 3 Functions MOVA [ Syntax ] MOVA src,dest [ Operation ] dest EVA(src) [ Function ] • This instruction transfers the affective address of [ Selectable src/dest ] src R0L/R0 R0H/R1 R1L/R2 A0/A0 A1/A1 [A0] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:16[A0] ...

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Chapter 3 Functions MOV Dir [ Syntax ] MOV Dir src,dest [ Operation ] Dir Operation HH H4:dest H4:src HL L4:dest H4:src LH H4:dest L4:src LL L4:dest L4:src [ Function ] • Be sure to choose R0L for either Dir ...

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Chapter 3 Functions MUL [ Syntax ] MUL.size src,dest [ Operation ] dest dest src [ Function ] • This instruction multiplies • If (.B) is selected as the size specifier (.size), and the result is stored in 16 bits. ...

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Chapter 3 Functions MULU [ Syntax ] MULU.size src,dest [ Operation ] dest dest src [ Function ] • This instruction multiplies • If (.B) is selected as the size specifier (.size), and the result is stored in 16 bits. ...

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Chapter 3 Functions NEG [ Syntax ] NEG.size dest [ Operation ] dest 0 – dest [ Function ] • This instruction takes the complement of two of [ Selectable dest ] [ Flag Change ] Flag ...

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Chapter 3 Functions NOP [ Syntax ] NOP [ Operation ] Function ] • This instruction adds 1 to PC. [ Flag Change ] Flag Change [ Description Example ] ...

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Chapter 3 Functions NOT [ Syntax ] NOT.size (:format) dest [ Operation ] ________ dest dest [ Function ] dest • This instruction inverts [ Selectable dest ] [ Flag Change ] Flag Change Conditions ...

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Chapter 3 Functions OR [ Syntax ] OR.size (:format) src,dest [ Operation ] dest src dest [ Function ] • This instruction logically ORs dest • and the selected size specifier (.size) is (.B), src ...

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Chapter 3 Functions [src/dest Classified by Format] G format src R0L/R0 R0H/R1 R1L/R2 A0/A0 *1 A1/A1 *1 [A0] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:16[A0] dsp:16[A1] dsp:16[SB] dsp:20[A0] dsp:20[A1] abs20 R2R0 R3R1 A1A0 *1 If (.B) is selected as the size specifier (.size), ...

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Chapter 3 Functions POP [ Syntax ] POP.size (:format) dest [ Operation ] If the size specifier (.size) is (.B) dest M(SP Function ] • This instruction restores [ Selectable dest ] [ Flag Change ...

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Chapter 3 Functions POPC [ Syntax ] POPC dest [ Operation ] dest M(SP dest *1 When when the U flag = 0 and [ Function ] • This instruction restores data ...

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Chapter 3 Functions POPM [ Syntax ] POPM dest [ Operation ] dest M(SP Number of registers to be restored [ Function ] • This instruction restores the registers selected by • Registers are ...

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Chapter 3 Functions PUSH [ Syntax ] PUSH.size (:format) src [ Operation ] If the size specifier (.size – 1 M(SP) src [ Function ] src • This instruction saves [ Selectable src ] src *1 ...

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Chapter 3 Functions PUSHA [ Syntax ] PUSHA src [ Operation ] SP SP – 2 M(SP) EVA(src) [ Function ] • This instruction saves the effective address of [ Selectable src ] src R0L/R0 R0H/R1 R1L/R2 A0/A0 A1/A1 [A0] ...

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Chapter 3 Functions PUSHC [ Syntax ] PUSHC src [ Operation ] SP SP – 2 M(SP) src *1 src *1 When when the U flag = 0 and [ Function ] • This instruction saves the ...

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Chapter 3 Functions PUSHM [ Syntax ] PUSHM src [ Operation ] SP SP – M(SP) src *1 Number of registers saved. [ Function ] • This instruction saves the registers selected by • The registers are saved ...

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Chapter 3 Functions REIT [ Syntax ] REIT [ Operation ] PC M(SP FLG M(SP Function ] • This instruction restores the PC and FLG values that were saved ...

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Chapter 3 Functions RMPA [ Syntax ] RMPA.size [ Operation ] *1 Repeat R2R0(R0 Until set to 0, this instruction is ignored. *2 Items in parentheses and followed by ...

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Chapter 3 Functions ROLC [ Syntax ] ROLC.size dest [ Operation ] [ Function ] dest • This instruction rotates [ Selectable dest ] [ Flag Change ] Flag Change Conditions S : The flag ...

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Chapter 3 Functions RORC [ Syntax ] RORC.size dest [ Operation ] [ Function ] dest • This instruction rotates [ Selectable dest ] [ Flag Change ] Flag Change Conditions S : The flag ...

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Chapter 3 Functions ROT [ Syntax ] ROT.size src,dest [ Operation ] C [ Function ] dest • This instruction rotates (MSB) are transferred to MSB (LSB) and the C flag. • The direction of rotation is determined by the ...

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Chapter 3 Functions RTS [ Syntax ] RTS [ Operation ] PC M(SP M(SP Function ] • This instruction causes control to return from a subroutine. [ Flag ...

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Chapter 3 Functions SBB [ Syntax ] SBB.size src,dest [ Operation ] dest dest – src – [ Function ] • This instruction subtracts dest • and the selected size specifier (.size) is (.B), src ...

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Chapter 3 Functions SBJNZ [ Syntax ] SBJNZ.size src,dest,label [ Operation ] dest dest – src if dest 0 then jump label [ Function ] • This instruction subtracts • If the operation results in any value other than 0, ...

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Chapter 3 Functions SHA [ Syntax ] SHA.size src,dest [ Operation ] src When < 0 src When > Function ] • This instruction arithmetically shifts ing from LSB (MSB) are transferred to the C flag. src • ...

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Chapter 3 Functions SHL [ Syntax ] SHL.size src,dest [ Operation ] src When < 0 src When > Function ] • This instruction logically shifts from LSB (MSB) are transferred to the C flag. • The direction ...

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Chapter 3 Functions SMOVB [ Syntax ] SMOVB.size [ Operation ] *1 When size specifier (.size) is (.B) Repeat M(A1) M Until set to 0, this ...

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Chapter 3 Functions SMOVF [ Syntax ] SMOVF.size [ Operation ] *1 When size specifier (.size) is (.B) Repeat M(A1) M Until set to 0, this ...

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Chapter 3 Functions SSTR [ Syntax ] SSTR.size [ Operation ] *1 When size specifier (.size) is (.B) Repeat M(A1) R0L Until set to 0, this instruction is ignored. [ Function ...

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Chapter 3 Functions STC [ Syntax ] STC src,dest [ Operation ] dest src [ Function ] • This instruction transfers the content of the control register indicated by location in the memory, specify the address in which to store ...

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Chapter 3 Functions STCTX [ Syntax ] STCTX abs16,abs20 [ Operation ] [ Function ] • This instruction saves task context to the stack area. • Set the RAM address that contains the task number in abs16 and the start ...

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Chapter 3 Functions STE [ Syntax ] STE.size src,dest [ Operation ] dest src [ Function ] • This instruction transfers src • and the selected size specifier (.size) is (.B), the operation is performed ...

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Chapter 3 Functions STNZ [ Syntax ] STNZ src,dest [ Operation ] then dest src [ Function ] • This instruction transfers [ Selectable src/dest ] src #IMM8 [ Flag Change ] ...

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Chapter 3 Functions STZ [ Syntax ] STZ src,dest [ Operation ] then dest src [ Function ] • This instruction transfers [ Selectable src/dest ] src #IMM8 [ Flag Change ] ...

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Chapter 3 Functions STZX [ Syntax ] STZX src1,src2,dest [ Operation ] then dest src1 else dest src2 [ Function ] • This instruction transfers dest . [ Selectable src/dest ] src #IMM8 [ Flag Change ...

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Chapter 3 Functions SUB [ Syntax ] SUB.size (:format) src,dest [ Operation ] dest dest – src [ Function ] • This instruction subtracts dest • and the selected size specifier (.size) is (.B), src ...

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Chapter 3 Functions [src/dest Classified by Format] G format src R0L/R0 R0H/R1 R1L/R2 A0/A0 *1 A1/A1 *1 [A0] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:16[A0] dsp:16[A1] dsp:16[SB] dsp:20[A0] dsp:20[A1] abs20 R2R0 R3R1 A1A0 *1 If (.B) is selected as for the size specifier ...

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Chapter 3 Functions TST [ Syntax ] TST.size src,dest [ Operation ] dest src [ Function ] • Each flag in the flag register changes state depending on the result of a logical AND of dest • ...

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Chapter 3 Functions UND [ Syntax ] UND [ Operation ] SP SP – M(SP) ( – M(SP) ( M(FFFDC [ Function ] • This instruction generates an undefined instruction interrupt. • The undefined instruction ...

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Chapter 3 Functions WAIT [ Syntax ] WAIT [ Operation ] [ Function ] • This instruction halts program execution. Program execution is restarted when an interrupt of a higher priority level than IPL is acknowledged or a reset is ...

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Chapter 3 Functions XCHG [ Syntax ] XCHG.size src,dest [ Operation ] dest src [ Function ] • This instruction exchanges the contents of dest • and the selected size specifier (.size) is (.B), the ...

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Chapter 3 Functions XOR [ Syntax ] XOR.size src,dest [ Operation ] dest dest src [ Function ] • This instruction exclusive ORs dest • and the selected size specifier (.size) is (.B), src operation ...

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Chapter 3 Functions Rev.2.00 Oct 17, 2005 page 134 of 263 REJ09B0001-0200 This page intentionally left blank. 3.2 Functions ...

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Instruction Codes/Number of Cycles 4.1 Guide to This Chapter 4.2 Instruction Codes/Number of Cycles Chapter 4 ...

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Chapter 4 Instruction Codes 4.1 Guide to This Chapter This chapter lists the instruction code and number of cycles for each op-code. An example illustrating how to read this chapter is shown below. Chapter 4 Instruction Code (1) (1) LDIPL ...

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Chapter 4 Instruction Codes (1) Mnemonic Shows the mnemonic explained in the page. (2) Syntax Shows an instruction syntax using symbols. (3) Instruction code Shows instruction code. Portions in parentheses ( ) may be omitted depending on the selected src/dest. ...

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Chapter 4 Instruction Codes/Number of Cycles ABS (1) ABS.size dest SIZE 1 .size SIZE . [An] [ Number of Bytes/Number of Cycles ] dest Rn ...

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Chapter 4 Instruction Codes/Number of Cycles (2) ADC.size src, dest SIZE .size SIZE . [An] [ Number of Bytes/Number of Cycles ] dest Rn An ...

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Chapter 4 Instruction Codes/Number of Cycles ADCF (1) ADCF.size dest SIZE .size SIZE . [An] [ Number of Bytes/Number of Cycles ...

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Chapter 4 Instruction Codes/Number of Cycles (2) ADD.size:Q #IMM, dest SIZE .size SIZE #IMM . [An] [ ...

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Chapter 4 Instruction Codes/Number of Cycles ADD (3) ADD.B:S #IMM8, dest DEST dest R0H Rn R0L dsp:8[SB] dsp:8[SB/FB] dsp:8[FB] abs16 abs16 [ Number of Bytes/Number of Cycles ] dest Rn Bytes/Cycles 2/1 Rev.2.00 ...

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Chapter 4 Instruction Codes/Number of Cycles (4) ADD.size:G src, dest SIZE .size SIZE . [An] [ Number of Bytes/Number of Cycles ] dest Rn An ...

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Chapter 4 Instruction Codes/Number of Cycles ADD (5) ADD.B:S src, R0L/R0H DEST SRC src R0L/R0H Rn dsp:8[SB] dsp:8[SB/FB] dsp:8[FB] abs16 abs16 [ Number of Bytes/Number of Cycles ] src Rn Bytes/Cycles 1/2 ADD ...

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Chapter 4 Instruction Codes/Number of Cycles (7) ADD.size:Q #IMM • The instruction code is the same regardless of whether (.B) or (.W) is selected as the size ...

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Chapter 4 Instruction Codes/Number of Cycles ADJNZ (1) ADJNZ.size #IMM, dest, label SIZE dsp8 (label code) = address indicated by label – (start address of instruction + 2) .size SIZE ...

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Chapter 4 Instruction Codes/Number of Cycles (1) AND.size:G #IMM, dest SIZE .size SIZE . [An] [ Number of Bytes/Number of Cycles ...

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Chapter 4 Instruction Codes/Number of Cycles AND (3) AND.size:G src, dest SIZE .size SIZE . [An] [ Number of Bytes/Number of Cycles ] dest Rn ...

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Chapter 4 Instruction Codes/Number of Cycles (4) AND.B:S src, R0L/R0H DEST SRC src Rn R0L/R0H dsp:8[SB] dsp:8[SB/FB] dsp:8[FB] abs16 abs16 [ Number of Bytes/Number of Cycles ] src Rn Bytes/Cycles 1/2 Rev.2.00 Oct ...

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Chapter 4 Instruction Codes/Number of Cycles BAND (1) BAND src src bit,R0 bit,R1 bit,Rn bit,R2 bit,R3 bit,A0 bit,An bit,A1 [A0] [An] [A1] [ Number of ...

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Chapter 4 Instruction Codes/Number of Cycles (2) BCLR:S bit, base:11[SB BIT [ Number of Bytes/Number of Cycles ] Bytes/Cycles 2/3 Rev.2.00 Oct 17, 2005 page 151 of 263 REJ09B0001-0200 4.2 dest code dsp8 ...

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Chapter 4 Instruction Codes/Number of Cycles BM Cnd (1) BM Cnd dest dest bit,R0 bit,R1 bit,Rn bit,R2 bit,R3 bit,A0 bit,An bit,A1 [A0] [An] [A1] Cnd ...

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Chapter 4 Instruction Codes/Number of Cycles (2) BM Cnd Cnd CND Cnd GEU GTU ...

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Chapter 4 Instruction Codes/Number of Cycles BNOR (1) BNOR src src bit,R0 bit,R1 bit,Rn bit,R2 bit,R3 bit,A0 bit,An bit,A1 [A0] [An] [A1] [ Number of ...

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Chapter 4 Instruction Codes/Number of Cycles (2) BNOT:S bit, base:11[SB BIT [ Number of Bytes/Number of Cycles ] Bytes/Cycles 2/3 (1) BNTST src ...

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Chapter 4 Instruction Codes/Number of Cycles BNXOR (1) BNXOR src src bit,R0 bit,R1 bit,Rn bit,R2 bit,R3 bit,A0 bit,An bit,A1 [A0] [An] [A1] [ Number of Bytes/Number of Cycles ...

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Chapter 4 Instruction Codes/Number of Cycles (1) BRK Number of Bytes/Number of Cycles ] Bytes/Cycles 1/27 • If the target address of the BRK interrupt is specified using the ...

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Chapter 4 Instruction Codes/Number of Cycles BSET (2) BSET:S bit, base:11[SB BIT [ Number of Bytes/Number of Cycles ] Bytes/Cycles 2/3 BTST (1) BTST:G src ...

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Chapter 4 Instruction Codes/Number of Cycles (2) BTST:S bit, base:11[SB BIT [ Number of Bytes/Number of Cycles ] Bytes/Cycles 2/3 (1) BTSTC dest ...

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Chapter 4 Instruction Codes/Number of Cycles BTSTS (1) BTSTS dest dest bit,R0 bit,R1 bit,Rn bit,R2 bit,R3 bit,A0 bit,An bit,A1 [A0] [An] [A1] [ Number of ...

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Chapter 4 Instruction Codes/Number of Cycles (1) CMP.size:G #IMM, dest SIZE .size SIZE . [An] [ Number of Bytes/Number of Cycles ...

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Chapter 4 Instruction Codes/Number of Cycles CMP (2) CMP.size:Q #IMM, dest SIZE .size SIZE #IMM . [An] ...

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Chapter 4 Instruction Codes/Number of Cycles (3) CMP.B:S #IMM8, dest DEST dest R0H Rn R0L dsp:8[SB] dsp:8[SB/FB] dsp:8[FB] abs16 abs16 [ Number of Bytes/Number of Cycles ] dest Rn Bytes/Cycles 2/1 Rev.2.00 Oct ...

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Chapter 4 Instruction Codes/Number of Cycles CMP (4) CMP.size:G src, dest SIZE .size SIZE . [An] [ Number of Bytes/Number of Cycles ] dest Rn ...

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Chapter 4 Instruction Codes/Number of Cycles (5) CMP.B:S src, R0L/R0H DEST SRC src Rn R0L/R0H dsp:8[SB] dsp:8[SB/FB] dsp:8[FB] abs16 abs16 [ Number of Bytes/Number of Cycles ] src Rn Bytes/Cycles 1/2 (1) DADC.B ...

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Chapter 4 Instruction Codes/Number of Cycles DADC (2) DADC.W #IMM16 Number of Bytes/Number of Cycles ] Bytes/Cycles 4/5 DADC ...

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Chapter 4 Instruction Codes/Number of Cycles (4) DADC.W R1 Number of Bytes/Number of Cycles ] Bytes/Cycles 2/5 (1) DADD.B ...

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Chapter 4 Instruction Codes/Number of Cycles DADD (2) DADD.W #IMM16 Number of Bytes/Number of Cycles ] Bytes/Cycles 4/5 DADD ...

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Chapter 4 Instruction Codes/Number of Cycles (4) DADD.W R1 Number of Bytes/Number of Cycles ] Bytes/Cycles 2/5 (1) DEC.B ...

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Chapter 4 Instruction Codes/Number of Cycles DEC (2) DEC.W dest DEST dest DEST Number of Bytes/Number of Cycles ] Bytes/Cycles 1/1 DIV (1) DIV.size #IMM b7 ...

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Chapter 4 Instruction Codes/Number of Cycles (2) DIV.size src SIZE .size SIZE . [An] [ Number of Bytes/Number of Cycles ] ...

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Chapter 4 Instruction Codes/Number of Cycles DIVU (2) DIVU.size src SIZE 1 1 .size SIZE . [An] [ Number of Bytes/Number of Cycles ] src ...

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Chapter 4 Instruction Codes/Number of Cycles (2) DIVX.size src SIZE .size SIZE . [An] [ Number of Bytes/Number of Cycles ] ...

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Chapter 4 Instruction Codes/Number of Cycles DSBB (2) DSBB.W #IMM16 Number of Bytes/Number of Cycles ] Bytes/Cycles 4/4 DSBB (3) DSBB.B R0H, R0L ...

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Chapter 4 Instruction Codes/Number of Cycles (4) DSBB.W R1 Number of Bytes/Number of Cycles ] Bytes/Cycles 2/4 (1) DSUB.B ...

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Chapter 4 Instruction Codes/Number of Cycles DSUB (2) DSUB.W #IMM16 Number of Bytes/Number of Cycles ] Bytes/Cycles 4/4 DSUB (3) DSUB.B R0H, R0L ...

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Chapter 4 Instruction Codes/Number of Cycles (4) DSUB.W R1 Number of Bytes/Number of Cycles ] Bytes/Cycles 2/4 (1) ENTER ...

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Chapter 4 Instruction Codes/Number of Cycles EXITD (1) EXITD Number of Bytes/Number of Cycles ] Bytes/Cycles 2/9 EXTS (1) EXTS.B dest ...

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Chapter 4 Instruction Codes/Number of Cycles (2) EXTS Number of Bytes/Number of Cycles ] Bytes/Cycles 2/3 (1) FCLR dest ...

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Chapter 4 Instruction Codes/Number of Cycles FSET (1) FSET dest dest DEST ...

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