R5F21244SNFP#U0 Renesas Electronics America, R5F21244SNFP#U0 Datasheet - Page 274

• Manufacturer Part Number: R5F21244SNFP#U0
• Description: IC R8C MCU FLASH 16K 52LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/24r

Specifications of R5F21244SNFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.2.00 Oct 17, 2005
REJ09B0001-0200
Chapter 5
Figure 5.3.3 Stack Status Before and After an Interrupt Request is Acknowledged
Figure 5.3.4 Operations when Saving Register Contents
5.3.3 Saving Register Contents
The register save operations performed as part of an interrupt sequence are executed in four parts 8 bits
at a time. Figure 5.3.4 shows the operations when saving register contents.
Note 1: When the INT instruction for software interrupt numbers 32 to 63 is executed, SP is indicated by
In an interrupt sequence, the contents of the FLG register and the PC are saved to the stack area.
The order in which these are saved is as follows. First, the 4 high-order bits of the PC and 4 high-order
bits (IPL) and 8 low-order bits of the FLG register, a total of 16 bits, are saved to the stack area. Next,
the 16 low-order bits of the PC are saved. Figure 5.3.3 shows the stack status before an interrupt
request is acknowledged.
If there are any other registers to be saved, use a program to save them at the beginning of the interrupt
routine. The PUSHM instruction can be used to save all registers, except SP, by a single instruction.
A d d r e s s
m–4
m – 3
m – 2
m – 1
m
m+1
Stack status before interrupt request is
acknowledged
MSB
the U flag. It is indicated by ISP in all other cases.
Content of previous stack
C o n t e n t o f p r e v i o u s s t a c k
Interrupts
Stack area
page 254 of 263
[ S P ] – 5
[ S P ] – 4
[ S P ] – 3
[ S P ] – 2
[ S P ] – 1
[ S P ]
N o t e 1 : [ S P ] d e n o t e s t h e i n i t i a l v a l u e o f t h e s t a c k p o i n t e r ( S P ) w h e n a n
LSB
A d d r e s s
i n t e r r u p t r e q u e s t i s a c k n o w l e d g e d . A f t e r t h e m i c r o c o m p u t e r
f i n i s h e s s a v i n g r e g i s t e r c o n t e n t s , t h e S P c o n t e n t i s [ S P ] m i n u s 4 .
[ S P ]
S P v a l u e b e f o r e
i n t e r r u p t r e q u e s t i s
a c k n o w l e d g e d
F L G H
S t a c k a r e a
FLG
P C
PC
M
L
L
PC
H
A d d r e s s
m–4
m – 3
m – 2
m – 1
m
m+1
Stack status after interrupt request is acknowledged
S e q u e n c e i n w h i c h o r d e r
r e g i s t e r s a r e s a v e d
MSB
( 3 )
( 4 )
( 1 )
( 2 )
F i n i s h e d s a v i n g r e g i s t e r s
i n f o u r p a r t s .
Content of previous stack
C o n t e n t o f p r e v i o u s s t a c k
F L G H
S a v e d s e p a r a t e l y , 8 b i t s a t a t i m e
Stack area
P C
F L G
P C
M
L
L
P C
H
L S B
5.3 Interrupt Sequence
[SP]
New SP value