R5F21244SNFP#U0 Renesas Electronics America, R5F21244SNFP#U0 Datasheet - Page 277

IC R8C MCU FLASH 16K 52LQFP

R5F21244SNFP#U0

Manufacturer Part Number
R5F21244SNFP#U0
Description
IC R8C MCU FLASH 16K 52LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/R8C/Tiny/24r
Datasheets

Specifications of R5F21244SNFP#U0

Core Processor
R8C
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
52-LQFP
For Use With
R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
R5F21244SNFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Part Number:
R5F21244SNFP#U0R5F21244SNFP#V2
Manufacturer:
Renesas Electronics America
Quantity:
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Company:
Part Number:
R5F21244SNFP#U0R5F21244SNFP#X6
Manufacturer:
Renesas Electronics America
Quantity:
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Rev.2.00 Oct 17, 2005
REJ09B0001-0200
5.6 Multiple Interrupts
Chapter 5
The internal bit states when control has branched to an interrupt routine are as follows:
By setting the interrupt enable flag (I flag) to 1 in the interrupt routine, interrupts can be reenabled so that an
interrupt request that has higher priority than the processor interrupt priority level (IPL) can be acknowl-
edged. Figure 5.6.1 shows how multiple interrupts are handled.
Interrupt requests that have not been acknowledged due to low interrupt priority level are kept pending.
When the IPL is restored by an REIT instruction and the interrupt priority is determined based on the IPL
contents, the pending interrupt request is acknowledged if the following condition is met:
• The interrupt enable flag (I flag) is cleared to 0 (interrupts disabled).
• The interrupt request bit for the acknowledged interrupt is cleared to 0.
• The processor interrupt priority level (IPL) equals the interrupt priority level of the acknowledged interrupt.
pending interrupt request
Interrupt priority level of
Interrupts
page 257 of 263
>
Restored processor interrupt
priority level (IPL)
5.6 Multiple interrupts

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