MC9S08DZ60ACLF Freescale Semiconductor, MC9S08DZ60ACLF Datasheet - Page 103

• Manufacturer Part Number: MC9S08DZ60ACLF
• Description: IC MCU 60K FLASH 4K RAM 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DZ60ACLF

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: S08DZ
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 2
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• For Use With: DEMO9S08DZ60 - BOARD DEMOEVB9S08DZ60 - BOARD EVAL FOR 9S08DZ60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load.
Because of this, the EMC emissions may be affected by enabling pins as high drive.
6.3
Port A, port B, port D, and port J pins can be configured as external interrupt inputs and as an external
means of waking the MCU from stop or wait low-power modes.
The block diagram for each port interrupt logic is shown
Writing to the PTxPSn bits in the port interrupt pin select register (PTxPS) independently enables or
disables each port pin. Each port can be configured as edge sensitive or edge and level sensitive based on
the PTxMOD bit in the port interrupt status and control register (PTxSC). Edge sensitivity can be software
programmed to be either falling or rising; the level can be either low or high. The polarity of the edge or
edge and level sensitivity is selected using the PTxESn bits in the port interrupt edge select register
(PTxES).
Synchronous logic is used to detect edges. Prior to detecting an edge, enabled port inputs must be at the
deasserted logic level. A falling edge is detected when an enabled port input signal is seen as a logic 1 (the
deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. A rising
edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a logic 1 during
the next cycle.
6.3.1
A valid rising or falling edge on an enabled port pin will set PTxIF in PTxSC. If PTxIE in PTxSC is set,
an interrupt request will be presented to the CPU. Clearing of PTxIF is accomplished by writing a 1 to
PTxACK in PTxSC.
6.3.2
A valid edge or level on an enabled port pin will set PTxIF in PTxSC. If PTxIE in PTxSC is set, an interrupt
request will be presented to the CPU. Clearing of PTxIF is accomplished by writing a 1 to PTxACK in
Freescale Semiconductor
PTxn
PTxn
PTxESn
PTxES0
Pin Interrupts
1
0
1
0
S
S
Edge Only Sensitivity
Edge and Level Sensitivity
PTxPS0
PTxPSn
Figure 6-2. Port Interrupt Block Diagram
MC9S08DZ128 Series Data Sheet, Rev. 1
PTxMOD
V
DD
D
CK
CLR
Q
Figure
INTERRUPT FF
PORT
6-2.
PTxACK
RESET
STOP
Chapter 6 Parallel Input/Output Control
SYNCHRONIZER
STOP BYPASS
BUSCLK
PTxIE
PTxIF
PTx
INTERRUPT
REQUEST
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